 Evaluated on the basis of:

Devices and their models

1

Course Flow!

Importance of course

Some required perquisite -device physics

Part-I Part-II

2

Course Flow!

How to extend LF Model to RF model ?

Device modeling exercises

Part-III

Seminar Talk!

 Evaluated on the basis of:

– Technical contents (T) – Logical flow (L)

– Presentation skill (P) – Question/Answer (Q)

 Presentation : 8-10 minutes

 Questions & Answers: 2-4 minutes

25 % 25 % 25 % 25 %

Mark Distribution

Prepare talk related to the subject areas !

Continue 26/11/2016

2pm onwards in UG Class room

Part-II: MOSFET devices &

their Models

 Level 1

– Known as Shichman-Hodges Model (1968).

– Accurate only for long channel devices

 Level 2: MOS2

– It incorporates second order effects e.g. CLM, Body Effect etc.

computationally complex.

 Level3: MOS3

– A semi-empirical model includes second order effects due to narrow width and short channel lengths

– Computationally efficient compared to Level2

 BSIM Model

– BSIM stands for Berkeley Short-channel IGFET Model.

 Other popular MOSFET Models:

– Philips MOS9, EKV, HiSIM etc.

BSIM Model Development

 BSIM 1

– Cover sub-micron MOSFET geometries

 BSIM2

– BSIM2 improves upon BSIM1 in terms of model accuracy as well as convergence behaviour in circuit simulation, however it breaks the transistor operation into several regions.

 BSIM3

– Widely used model for CMOS IC Design

– Single-equation to describe device characteristics in the various regions of operation.

 BSIM4

– Include parasitics at rf, which BSIM3 ignore – Used for high frequency Applications

– With improve rf Modeling capability

BSIM Model Development

 BSIM 5

– Model for aggressively scaled (e.g. 45 nm ) MOSFET – Incorporate more detail physics

– Provide unified formulation the device in various region of operation

 BSIM6

– Released in year 2014

– The model provides excellent accuracy in all regions of operation.

 Others Models – BSIM-SOI – BSIM-CMG

HA:

Prepare a brief report of 1-2 pages on Various stages of BSIM Models development

Ref: http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG

BSIM3 Model – A critical Look

 It is a physics-based, accurate, scalable, robust and predictive MOSFET SPICE model for circuit simulation

 It adopts a single-equation to describe device characteristics in the various operating regions, which eliminates the discontinuity in the I-V and C-V characteristics.

 There are three versions of this model e.g. BSIM3v1, BSIM3v2 & BSIM3v3.

There are several variations within BSIM3v3 itself, which include BSIM3v3.1 BSIM3v3.2, and BSIM3v3.3 .

 It is a charge-conservative model, where the sum of currents flowing into the four terminals of the MOSFET is zero.

 The model is physical, with most parameters having strong correlation with the fabrication process. However, some of the parameters have weak physical significance and are introduced mainly for the purpose of fitting.

 A variety of short-channel effects are included in the model like charge-sharing effects, drain-induced barrier-lowering, reverse-short-channel effects, and those effects found in short-channel and narrow-width devices

Cont..

 BSIM3 is adequate for a majority of analogue and digital circuit simulation.

However, for rf applications, a sub-circuit approach to include parasitic elements is required.

 BSIM3 accounts for the parasitic such as overlap and (outer) fringing capacitances as well as the bulk-source and bulk-drain diodes

Web Page: http://www-device.eecs.berkeley.edu/~bsim3.

The source and drain terminal resistances are included in BSIM3, but not the gate to substrate resistances. Likewise, the noise associated with the gate and substrate resistances are not included.

 All voltages in the BSIM3 are referenced to the source terminal, not to the bulk.

 It accounts for the first-order effects of temperature on the device characteristics. The degradation of the mobility and increase of threshold voltage with temperature are modelled.

 CapMod=0 in the BSIM3 for the intrinsic transistor is based on long-channel approximation. Many of its device capacitances can exhibit incorrect voltage dependencies, although the circuit simulation can still be quite accurate.

What BSIM3 does not include?

 It does not include self-heating effects. The device temperature, once specified, remains constant during the entire simulation. It is possible to specify the device temperature to any particular value. BSIM3 contains the parameters to calculate the proper device characteristics under various temperatures.

 The model does not include the drain-induced gate noise. Only the thermal noise and the 1/f noise of the channel are considered.

 BSIM3 does not include the gate-oxide tunnelling current through oxide.

In means that dc gate current is identically zero. There is no leakage path between the gate and other terminals. However, the only leakage currents included in BSIM3 are those associated with drain-bulk, the source-bulk junctions, and the substrate current brought about by impact ionisation.

 When gate-to-source voltage V_GS is zero or negative, the sub-threshold current continue to decrease exponentially towards zero as V_GS decreases, even when V_GS become negative. i.e. BSIM3 can be used to predict the OFF current (the drain current at zero V_GS)

 There is no parameter which specifies the maximum operating voltages for V_GS, V_DS and source-to-bulk V_BS.

 Care must be exercised to ensure that the voltages lie within the breakdown values.

In developing a model the mathematical formulation is used to describe the transistor behaviour. A circuit designer, in contrast, prefers to visualize a transistor with its equivalent circuit. In the following sections, equivalent circuits based on BSIM3’s mathematical formulation will be described. It includes equivalent circuits for dc, large-signal, small-signal ac, and noise analysis.

What BSIM3 does not include?

Types

I-V

Dynamic

(Include energy storage

elements) Noise

Model Formulation

Modelling is defined as the process by which the electrical properties of a semiconductor device are represented by means of mathematical equations, circuit representations

How equation for these models are formulated ?

Ref: Y. Cheng et. al. , MOSFET Modeling & BSIM3 User Guide

dc I-V

The dc model used in BSIM3 is shown here.

IDS

I_sub

R_D

G_MIN R_S

GMIN

Source Drain

Gate

Bulk

SB

Ij_,

  I_j,DB

dc model does not account for any leakage current between gate and channel.

Ref: Y. Cheng et. al. , pages: 106-141

dc I-V

• i.e. in BSIM3, there is a complete dc open circuit between the gate and the other side of the oxide.

• The dc gate current is always zero.

• It add G

(default value 10



) across drain- bulk and the source-bulk just to aid convergence

• These conductances do not bear physical significance but they added purely to aid convergence of numerical solution during computer iteration.

• I

& I

are modelled

by a normal diode

equation.

Cont…

• The source resistance R

and drain resistance R

are included and modelled based on sheet resistance of the source and drain contacts.

• The drain-to-source current I

incorporates short-channel effects and is generally a complex function of voltages.

• The I

can be formulated based on channel charge

density and the velocity-field relationship.

Channel Charge

gsteff OX

chso C V

Q 

When V

=0, the channel charge Q

can be written as:

V

become V

-V

in the strong inversion, and follows an

exponential relationship in the sub-thresold region.

Cont..

When V

is applied unified charge, Q

can be expressed as:

) 1

( ^{( )}

) (

b y F chso

y

chs V

Q V

Q  

bulk t gsteff

b A

nv V V

Where 



 Abulk is a parameter accounting for the bulk charge effect due to V

 V

stands for the quasi-Fermi potential at any given

point, y along the channel with respect to the source.

Velocity-Field

The velocity and electric field is related through the equation:

sat y

y

y E E E

v_{( )}    v_(y)  v_sat E_y  E_sat

Where  is the mobility including the influence of the lateral electric field E_yand is given by

) 1

/(

sat y

eff E

 E

 



Where _eff is the effective mobility, which is complex function gate bias and body bias

Now, combining mobility and charge expressions, Id valid in different regions can be expressed as:

dy Q dV

W

I_d(y)  _{eff chs(y)} ^F(y)

Assuming R_ds = 0 and integrating the above equation from source (i.e. y=0 ) to drain (i.e. y=L_eff ), the drain current, I_ds0 expression valid from sub-threshold to strong inversion region can be written as:

Cont..

) 1

(

2 ) 1

0 (

0

eff sat

DS eff

b DS DS

chs eff eff ds

L E L V

V V V

Q W

I









When R_ds>0 , I_DS can be modified as :

DS ds ds ds DS

V I R I I

0 0

1



Now when R_ds>0 and SCEs are carefully accounted, then I_DS current valid from sub-threshold to the strong inversion region can be derived as:

) 1

)(

1 (

1 ^{0( )}

) ( 0

ASCBE dsat DS

A dsat DS

dsat Vdsat ds ds

Vdsat ds

DS V

V V

V V V

V I R

I I    





Where V_dsat is the saturation voltage. V_A and V_ASCBE are the Early voltages accounting for various short-channel effects.

Dynamic Formulation

• Before proceeding to the discussion of BSIM3 dynamic formulation used for transient and ac analysis, it is instructive to examine the various device capacitances, which play an important role in MOSFET dynamic performance.

• Generally, MOSFET capacitance can be divided into two groups, intrinsic and the extrinsic capacitances.

• The intrinsic capacitance

is related to the region

between the metallurgic

source and drain

junctions.

Cont..

Intrinsic Capacitance

Extrinsic Capacitance Extrinsic

Capacitance

Cont…

• Extrinsic capacitance, or the parasitic capacitance, which include bulk-drain and bulk-source diodes can be broadly grouped in three categories as follows:

– The fringing capacitance between the poly-silicon gate and source (taken identical to gate-drain fringing capacitance), C

; – The overlap capacitances between the gate and source

( taken identical to gate-drain overlap capacitance), C

;

– Drain-bulk junction capacitance, C

and source-bulk junction

capacitance, C

.

Cont…

• These parasitic capacitances are reciprocal. If C

denote the parasitic gate-source capacitance, define as Q

/

V

where Q

is the portion of the gate charge associated with the parasitic capacitance.

• The reciprocal nature of the parasitic capacitance means that C

is the same as C

which is Q

/ V

.

• Similarly, other inter electrode parasitic capacitances can be defined as:

DB j p

db p

bd

f ov

p dg p

gd

C C

C

C C

C C

, ,

,

, ,











DB j p

sb p

bs

f ov

p sg p

gs

C C

C

C C

C C

, ,

,

,

,











0 ,

,p bg p gb

gb C C

C  

• The remaining capacitances

C

, C

and C

are the

device intrinsic capacitances

as shown in the figure in bold

face. The total gate-to-source

C

, gate-to-drain C

and

gate-to-body C

can be

expressed as:

Cont…

f ov

i gd t

gd C C C

C _,  _,   C_gb,t  C_gb,i C_gb0

T

dt dv v

Q dt

dv V

Q dt

dv v

Q dt

t dQ

i ^BS

BS G DS

DS G GS

GS G G

G 

 



 



 

 ) (

dt dv v

Q dt

dv v

Q dt

dv v

I Q I

I t

i ^BS

BS DS Deff

DS GS Deff

GS Deff DB

j sub DS

D 

 



 



 





 _,

) (

dt dv v

Q dt

dv v

Q dt

dv v

I Q I

I t

i ^BS

BS DS Beff

DS GS Beff

GS Beff DB

j SB j sub

B 

 



 



 







 _{, ,}

) (

Where Q_G is the total gate charge, Q_Deff = Q_D - Q_J,DB is the total effective drain charge and Q_Beff = Q_B + Q_J,DB +Q_J,DS is total effective bulk charge.

These equations can be solved and branch currents and voltages can be determined.

Ref: Y. Cheng et. al. , MOSFET Modeling & BSIM3 User Guide

Noise Formulation

• A useful measure of the noise performance of a system is noise factor, usually denoted by F.

The noise factor F and noise figure NF are defined as:

• Presented below the most significant noise sources associated with the MOSFET, which have been suitably modelled to accommodate the sub- micron characteristics.

source the

to due power

noise output

Total

power noise

output Total

F 

(F) log

10 (NF)

Figure

Noise  

Cont…

• Channel thermal noise is the most important noise source. In order to calculate its value the channel is separated into two regions:

– One where the gradual channel approximation holds

– Another where carrier velocity saturation is present.

• The fundamental theory to calculate the channel noise

• Gamma factor () equals 2/3 for the classical theory but it deviates toward larger values for short channel devices.

0 2

4 _{B d}

d k T g

f

i  



Where k_B is the Boltzmans constant,  is a factor which strongly dependent on bias, and g_d0 is the zero-bias drain conductance.

Cont…

• Induced gate noise, which is insignificant for large device. However, it dramatically increase as

the frequency of

operation is increased in GHz range.

• Gate resistance R

noise is contributed due to gate material used and modelled in BSIM3 as:

• Substrate resistance and series drain/source resistances also produce noise in a device, which need to be carefully modelled with.

• While series drain/source resistances can be kept low by increasing doping, however the contribution of the back-gate effect e.g. substrate resistance is very critical.

4 3

2 R f

T k

v_g  _B ^g 

• As regards noise model in BSIM3, the thermal noise is definitely accounted for.

• The induced gate noise and gate noise are not available in BSIM3 and should be accounted at microwave frequency of operation.

• For the substrate noise contribution is absent in BSIM3 but thermal noise due to source resistance is incorporated

• The proper way to include the terminal resistances, as far as noise analysis is concerned, is to declare the source and drain resistances through the sheet resistance parameters.

• The noise equivalent circuit adapted in BSIM3 is shown in the Figure.

• BSIM3 considers the parasitic junction diodes to be noise free.

BSIM3--Noise Modeling

Cont..

Therefore, there are no noise sources associated with g

and g

,

which are the conductances of the junction diodes. There is no noise

source associated with G

, either. The conductance G

is added to

aid numerical convergence.

29

Optimization of F

MOSFET

Y_S F

~ Source

Source admittance

OPT S

OPT S

MIN i.e.B B &G G F

F   

MOSFET

Y_OPT

F

~ Source

Source admittance

With Y_OPT F=F_MIN

Y

for MOSFET can be expressed as:

   





2 S

s n

MIN G B

G F R

F   G_OPT   B_OPT

See TH Lee for detail

 

  _



 



 







T 2

T

MIN

ω

2.3 ω 1

c - 1 ω γδ

ω 5 1 2

F ~





gs

OPT

1 - c

5γ αωC δ

G  ^B

^{ 0}

Cont..

Minimizing the noise is qualitatively similar to maximizing power transfer, however the source admittances leading to these two conditions are almost never the same.

Therefore, one generally can not enjoy maximum power

gain and minimum noise figure simultaneously.

Concluding Remarks

• Introduced the industry standard model, BSIM3

• Mathematical formulation for dc, dynamic and noise have been covered

• BSIM3 as such is not suitable for rf

applications without incorporating

parastics especially around gate and

substrate.

32

Course Flow!

How to

extend BSIM3 Model for RF ?

Part-III

Ref:

M.S. Alam, and G.A. Armstrong, Accurate Substrate Modelling of RF CMOS, International Journal of Numerical Modelling, Volume 19, Issue 3 May/June 2006, pp 257-269.

M. S. Alam, and G.A. Armstrong, Extrinsic Resistance Parameter Extraction and RF Modelling of CMOS, Solid State Electronics, Elsevier Publication, Volume 48, Issue 5, 2004, pp. 669-674.

33

RF Model

 A MOSFET is a good candidate for RF IC application because of its low cost and high integration potential.

 As the gate-length of a MOSFET reduces, its high frequency characteristics improve.

 The BSIM3 model has been used successfully as an accurate and scalable silicon MOSFET model in the low frequency range (<1GHz).

 One of the powerful strategy is to extend

BSIM3 for rf is to add relevant parasitics

especially around gate and substrate .

34

RF Model

Substrate Network R_g

Intrinsic Model

B G

D

Gate and substrate parasitics are accounted

But for simplicity they have been modeled as a lumped elements

R

R

+ R

Gate Resistance

Distributive

>1GHz

Signal of frequency >1GHz at the gate not ONLY see the R

but R

also influence and they are distributive in NATURE

R

is a complex combination of R

and R

Significant bearing on input impedance and noise.

See page 87 of Ytterdal Book!

 Substrate parasitics are not important <1GHz.

 Distributed in nature but can be approximated using lumped components.

 Contribute significantly to output admittance (20%) and affect noise at rf.

Substrate Parasitics

Among various models , 3-elements model is more popular

3-elements Model



R

= Model source-bulk signal activity



R

= Model drain-bulk signal activity



R

= Signal activity along the channel

db

dsb

R

R 

sb

dsb

R

R 

db sb

SUB

R R

R 

R_SUB

Cont..

At GHz, normally source is connected to the body and grounded

If R_S is of low value

 





SUB

j C R j C R

C j R

C y j













  1

1

C_sb

C_db

R_SUB R_S

……

B

R_D

S D

……

C_sb

C_db

R_SUB R_D

D

Common S/B

Y_SUB

Cont..

sb

SUB

sC

R  1

sub db

db

SUB

j C R

C y j

1

~ 



 

C_sb

C_db

R_SUB

Common S/B

Y_SUB

C_db

R_SUB

Y_SUB

i.e. most of the signal activity is

confined to R

g_mbV₂ V₁

Core

RF Model

Parasitics

Parasitics have NOW been

identified !

They have been modeled through

resistive elements and they

g_mbV₂

V

R

C

R

R

R

rf Model (>1GHz)

Core Model (<1GHz)

BSIM3 + ^{Parasitics rf}

Question?

The model is not know as its components are NOT known!

These components are determined by a technique called EXTRACTION

Step-I

Measured S-

Parameters of the DUT

Step-II

Convert S to Y or Z or H

Step-III

 Use appropriate EC

 Carry out small-signal analysis

 Express model elements in terms of known Ys or Zs

Following steps are involved:

g_mbV₂ R_G

V₁ C_db

C_SUB

V

G

S

S/D heavily doped!

Simplified Model !

R

=R

0

1 m

V g C

C

V

G

S

D

g

V g

V

R

C

R

V_S

I

I

Analysis

V

=0

2 0

11

SC

S S V

y I

V



11 _g

(

) (

)

y   R C  C  j  C  C

Under the assumption ² (C_gd+ C_gs)² R_g²  1

1

2 0

2 21

SC

SC S V

y I

V



21 _m

-

y  g j C 

If  <<1/ R_g(C_gd + C_gs)

2 Carefully look at these

equations and express model elements in terms of Ys

1 m

V g C

C

V

G

S

D

g

V g

V

R

C

R

V_S

I_s I_1SC

Analysis

V_1SC=0

12

-

y  j C 

If  <<1/ R_g(C_gd + C_gs)

1 0

1 12

SC

SC S V

y I

V



3

1 0

22

SC

S S V

y I

V



Under the assumption that ² R_sub²C_db²1

2 2

Re( y

)  g

  C R

(1  g R

) Im( y )   C

  C

(1  g R

)

Carefully look at these

Equation and express model components in terms of Ys

22 0

ds

Re( y )

g



Using (1)

2 11

11

g

(Im( y ))

) y

R  Re(

g

 Re( y

)

Im(

)

gd

C y

  

Using (3)

 ^{0.1 0.2} 

mb m

g   g

Im(

)

gs gd

C y C

  

Using (1)

Extraction Result

g_mbV₂ R_G

V₁ C_db

R_SUB V₂ G

S Known

Unknown

Going through various steps involved for EXTRACTION

Elements shown in green enclosure have been determined but BLUE enclosure elements are not known yet!

2 2

Re( y

)  g

  C R

(1  g R

) Im( y

)   C

  C

(1  g R

)

Defining Equation!

)) y

Im(

) y (Im(

R

g )

y C Re(

12 22

sub

ds 22

db

 



-

) g

) y

(Re(

g ))

y Im(

) y (Im(

g )

y R Re(

ds 22

mb 2

12 22

ds 22

sub

-

-



 

Re-Cap!

Taking you through various steps involved in EXTRACTION

What if source & drain are not heavily doped?

There effect need to be carefully included !

g_mbV₂

R_S

R_G R_D

V₁

Improved Model

C_db

C_SUB V₂

Known

Unknown

Unknown

Components in GREEN enclosure are known Components in BLACK enclosures are NOT known

How to determine components in BLACK enclosure?

g_mbV₂

R_S

R_G R_D

V₁

Analysis

C_db

C_SUB V₂

2

V_S

I_s

1

V_1OC

12 2 2 2

Re( ) _s BC^gd

Z R

A B

 





1 0

1 12

OC S I

Z V

I 



22 2 2 2

( )

Re( ) _{s d} C^gs C^gd B

Z R R

A B



   

1 0 

22

s s I

Z V

I 



Where A and B are constant

Source Resistance R _S



  As

0

B A

R BC )

Z

Re(

 

 

Re (Z

)



R_S

R

 Re( Z

)

Asymptotic plot of Re(Z12) gives the value of Rs

Re (Z

)



R_D+R_S

2 2

2

gd gs

d s

22

A B

B ) C

C R (

R )

Z

Re( 

 



 



  As

0

Re(

)

S D

R  R  Z

Drain Resistance R _D

Asymptotic plot of Re(Z22) gives the value of Rs+Rd With Rs already known; Rd can be determined

g_mbV₂

R_S

R_G R_D

V₁

RF Model

C_db

C_SUB V₂

Model is known

R_G=5 C_gs= 100fF C_gd = 30fF g_ds= 0.01mS g_m =0.1mS g_mb=0.01mS R_S=R_D=4 Typical value for CMOS process

g_mbV₂

R_S

R_G R_D

V₁ C_db

C_SUB V₂

Question?

Which of the model elements contribute to the noise?

Various parasitics PLUS e-activities in the channel

g_mbV₂ R_G

V

R_SUB

V

Problem!

Cds

For the given model, show that

2 SUB 2

db 2

db gd

22

ds

1 C R

C C )

y C Im(



 

 



V_S

I

I

V

=0

2 2

2 2

22 2 2 2 2 2 2

1 1

db sub db

ds gd g gd ds

db sub db sub

C R j C

y g C R j C j C

C R C R

    

 

     

 

Under the assumptions 

(C

+ C

)

R

 1 and 

R

C

 1, y

can be simplified to:

1 0

22

SC

S S V

y I

V



Hint: Use imaginary part

Solution!

 Importance of model has been explained.

 Various steps involved in how to develop rf model have been covered.

Concluding Remarks

Ending Style