IC Processing Technologies
FUNDAMENTAL CONSIDERATIONS FOR IC PROCESSING
IC PROCESSING:
• is the process of building devices in a single piece of silicon crystal
• is a process of building successive layers of insulating, conducting, and semi- conducting material.
• each layer is patterned to give a distinct function and relationship with surrounding areas and subsequent layers.
• the layers are produced and patterned by various techniques.
Major IC technologies that are used today are
• n-channel metal-oxide - semiconductor (NMOS),
• complementary metal-oxide-semiconductor (CMOS),
• bipolar, and
• integrated Injection-logic bipolar (I
2L).
in order of increasing complexity of the processing.
Major IC technologies
• Figure 1 shows important ways to create a layer in or on the silicon crystal.
• The layers are formed by - oxidation,
- implantation, - deposition, or by
- epitaxial growth of silicon.
• Each one of these layers can be formed :
- uniformly, as shown in the left side of Fig. 1, or
- selectively, as shown in the right side of the, figure.
Building Individual Layers:
FIGURE 1
Schematic representations of forming layers in silicon:
(a) uniform, (b) selective.
Fabrication processes involved in Major IC technologies
(a) (b)
1) The oxidation technique chosen depends upon - thickness and
- oxide properties required.
-if thin oxides are required then it should be grown in dry oxygen in Si.
-If thick oxides(>0.5μm) are desired, then steam is used (~1 atm or an elevated pressure of upto 25 atm).
2) if an insulating layer is needed,
- oxidation of silicon forms a layer of Si0
2, which is an excellent insulator and can be formed with a high degree of uniformity.
- the formation of the Si0
2layer consumes silicon and may require relatively long thermal cycles for thicker layers.
3) if a thick insulating oxide is needed,
- it requires an oxide deposition of polycrystalline silicon.
Patterning of the layers for selective formation achieved by using - photolithography and
- etching
The various techniques chosen for forming individual layers is
according to their usefulness for particular applications.
• The deposited oxide has
- a poorer uniformity than the thermally grown oxide - but can be deposited at much lower temperatures.
• Analysis must be made at each step in the process development
to determine which type of layer will give desired results without adversely affecting previous layers.
• Oxidation and deposition are the most common ways of forming a dielectric layer .
- The oxidation can be made selective by depositing and patterning Si
3N
4before oxidation,
- allows the oxide to form only wherever the Si
3N
4is removed, since the Si
3N
4blocks the oxidation.
- This technique is called “local oxidation.”
Polycrystalline silicon, also called polysilicon, is a material consisting of small silicon crystals. It differs from single-crystal silicon, used for electronics and solar cells, and from amorphous silicon, used for thin film devices and solar cells.
The main advantage of polysilicon over a-Si is that the mobility can be orders of magnitude larger and the material also shows greater stability under electric field and light-induced stress.
Integrating the Process Steps: The process of building a succession of layers requires careful consideration of each layer‟s relative position to the others.
• Fundamental components of all transistors are:
-The junctions formed by n-type and p-type doped regions
-The doping levels and depths of these doped regions determine the characteristics of the devices.
• Ion implantation is the most important doping technique in modern ICs.
- The ion- implantation techniques and the techniques used for diffusion of the dopants determine the doping profiles.
-Selective doping, as shown in the middle of Fig. 1b, can be achieved using a variety of masking layers such as photoresist, polysilicon, or Si0
2.
• Deposition of materials can be achieved through the CVD methods
- choice of material depends on the particular application and function - most common materials being :
silicon oxides, polysilicon, aluminum, and silicon nitride.
- Some deposited materials can be deposited selectively, as shown in the bottom of Fig. 1b, which may give an advantage for some applications.
• Epitaxial growth of single-crystal silicon is deposited uniformly or selectively.
- Selective epitaxial growth is not used commonly in ICs but has many advantages that may be useful for future devices.
IC Fabrication Processes: Fundamental Components and Formation Procedures
The process sequence for n-channel or metal-oxide-semiconductor (NMOS) technology is the least complex because it requires the least number of lithography levels.
In addition, the fundamental aspects of the NMOS technology are also important for 1. CMOS technology
2. MOS memory technologies.
NMOS IC TECHNOLOGY
• The basic n-channel circuit consists of NMOS transistors.
• Each NMOS transistor
-consisting of a source, a drainand a gate region.
-is isolated from its neighbors by a thick field oxide.
• The basic device structure is shown in Fig. 1.
• The device is covered with an insulating layer of phosphorus-doped Si02, called P-glass.
• The device has a layer of dopant under the field oxide, -called the channel-stop region,
-serves to improve the isolation between transistors.
• The NMOS transistor operates by
-causing a negative charge to move
-from the source to the drainin response to a positive charge on the gate.
-If the charge on the gate is sufficient
-increases the source-to-gate voltage above a threshold voltage VT, -electrons are attracted to the region under the gate
-forms conducting path between drainand source.
• Inmost applications, two kinds ofNMOS transistors areused:
-enhancement mode devices (EMD) -depletion mode devices (DMD).
-enhancement mode device has aVT > 0 -depletion mode device has aVT < 0.
Fig. 1
NMOS Transistor
Top View and Cross-Section
• N-Channel Metal-Oxide Semiconductor Transistor
• n- and p-type semiconductor regions
• Thick and thin oxides
• Etching Openings
• Polysilicon gate
• Metal (Al) Interconnections
Conducting Channel Region
Figure 1
Basic NMOS Process Key Steps
•Oxidation
•Photolithograph y
•Implantation
•Diffusion
•Etching
•Film Deposition Process involved
Polysilicon-gate is doped with phosphorus to minimize mobile ion contamination, resulting in faster switching speeds and better control of threshold voltage
Thin padding layer
Starting material.
Virtually all MOS technologies use silicon waferswith the crystal surfacein the <100> orientation. This <100> orientation is preferred over the <111>
orientation because it introduces about 10 times less interface trap density, which can cause charging at the Si02-silicon interface. This charging causes variations in the threshold voltage of the devices and is therefore
undesirable. For most NMOS technologies, the siliconwill be lightly doped p-type(~1015atoms/cm3).
NMOS Fabrication Process
(a) Grow “thin-pad” layer of SiO2 and deposit Si3N4layer by CVD.
(b) (1) Mask #1 -- Photolithography and etching to define the active NMOS transistor areas.
Remove SiO2and Si3N4everywhere else by etching.
(2) Then do boron ion implantation (“field implant”).
This improves isolation of neighboring transistors from one another.
(c) (1) Grow thick oxide (“field oxide”) outside the transistor areas.
(2) Remove Si3N4and thin pad SiO2by etching.
(3) Grow thin “gate oxide” (the oxide that will separate the polysilicon gate from the transistor channel.
(4) Ion implant boron to adjust the transistor threshold voltage to the desired value (gate voltage needed to turn on the transistor).
(5) Deposit polysilicon (CVD) over entire wafer.
(d) (1) Mask #2 -- Photolithography and etching to define the polysilicon gate regions and interconnections.
Remove poly everywhere else by etching.
(2) Ion implant arsenic or phosphorus to dope the source and drain regions and the polysilicon gate material (n-type).
(3) The implanted dopant is “activated” and usually driven deeper into the wafer with a high temperature diffusion step.
(e) (1) Deposit protective oxide (SiO2) by CVD.
(2) Mask #3 -- Photolithography and etching to open contact windows.
(f) (1) Deposit metal (aluminum) over entire wafer surface by sputtering or evaporation.
(2) Mask #4 -- Photolithography and etching to pattern the aluminum metal layer to produce the desired metal interconnection pattern.
Etch away the aluminum where it is not wanted.
(g) Not Shown
(1) Deposit a passivation (protective) layer of phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) over the entire wafer surface.
(2) Mask #5 -- Photolithography and etching to open windows in the PSG or BPSG passivation layer so bonding wires can be attached to the aluminum “bonding pads” on the periphery of each IC die.
(h) Not Shown
(1) Individual IC dice are separated from one another by sawing or by scribing and breaking the wafer.
(2) Each IC die is attached to a package or “header” with an epoxy adhesive or a metal alloy solder.
(3) Wire bonding is the most common method for making electrical connections between the aluminum bonding pads on the periphery of each IC die and the package.
• There are several important features of this NMOS fabrication process:
There are 5 mask steps.
Each of these mask steps uses a “subtractive” (etching) process.
i.e., the entire surface of a wafer is first coated with the desired material.
then, the material is removed from areas where it is not wanted by wet chemical etching or plasma (dry) etching.
Additional insulating layers, metal layers, and mask steps can be added to enable more complex interconnection of transistors.
Bipolar Technology
Characteristics of Bipolar Technology
Higher switching speed
Higher current drive per unit area, higher gain
Generally better noise performance and better high frequency characteristics Better analogue capability
Improved I/O speed (particularly significant with the growing importance of package limitations in high speed systems).
high power dissipation
lower input impedance (high drive current) low voltage swing logic
low packing density
low delay sensitivity to load high g
m(g
m Vin)
high unity gain band width (f
t) at low currents essentially unidirectional
Advantages of Bipolar over CMOS
Other Bipolar Advantages
Bipolar IC technology preferred technology for high-speed applications. Why?
- Because in this technology transit time depends on the base width of the bipolar devices.
-The base width -is not determined by lithography (as is the channel length of MOS devices) - is determined by distance/difference between two impurity diffusion profiles.
-this distance can be precisely controlled and - base-width can be made very thin,
- allows high- speed operation of the bipolar transistors.
The processing of bipolar devices is more complicated than the MOS process sequences.
The complication arises because of the need to form a buried layer of dopant by growing an epitaxial layer of silicon on a patterned and doped silicon substrate.
Figure
Three dimensional view of oxide-isolated bipolar transistor.
Modern bipolar IC technology uses a thick silicon dioxide layer to electrically isolate the individual transistors.
Fig. 1 shows :The resulting device cross
section of an oxide isolated bipolar
transistor.
Starting material :
• Starting material for these devices is a lightly doped p-type substrate with either a <111> or a <100> crystal orientation.
Buried layer and Epitaxial layer : Why ?
• Transistors must have high breakdown voltage of collector.
• This requires high resistivity material,
but high resistivity coupled with thickness of wafer (in earlier technology) ---- -results in excessive collector resistance that
-limits high frequency response - increases power dissipation.
Solution of this problem
• Epitaxial growth of a high-resistivity layer on a low-resistivity substrate
• The substrate and epitaxial layer have opposite doping types to provide isolation.
• In between them is a heavily doped diffusion layer called the „Buried layer‟.
Bipolar Technology Process
-Buried layer‟s sheet resistance should be as low as possible to reduce
collector resistance of transistor . Process of Buried layer Formation:
-implanting arsenic or antimony through windows etched in a thermal oxide -forming the heavily doped n + region of the collector.
-implanted layer is driven into the substrate in an oxidizing ambient -“buried layer.‟ is formed
-All oxide is then stripped and an n-epitaxial layer is grown on the substrate.
Buried layer Step Formation & its Use Because of different rates of oxidation
-between exposed buried layer and surrounding area, a step is formed at the buried layer edge.
The step in the buried layer
-propagates up through the epitaxial layer -serves as an alignment mark
for the next lithographic level (Fig. a).
Buried layer: heavily doped diffusion layer -serves as a low resistance collector contact.
step
Buried layer mask
Buried layer=Heavily doped n+ layer
Bipolar Technology
Bipolar Transistor
Top View and Cross-Section
• Bipolar Junction Transistor (BJT)
• Standard Buried Collector Process (SBC)
• n- and p-type semiconductor regions
• Thick and thin oxides
• Etching Openings
• Metal (Al) Interconnections
Active Transistor Region
Figure 1.
Standard Buried Collector Process (SBC Process ): Key Steps
•Oxidation
•Photolithography
•Implantation
•Diffusion
•Etching
•Film Deposition
