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Performance-aware test-time optimization schemes for analysis of logic level faults in channels of on-chip networks


Academic year: 2023

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202 6.7 Application of the proposed test scheme in the first subnet of the 3×3 network. a) Execution of the test algorithm at odd nodes and analysis of test responses at even nodes. 209 6.9 Online evaluation of the proposed solution to observe the behavior of different . performance measurements in 3×3 NoC with 16-bit channels.


SoC Integration and Its Challenges

SoC to NoC: A Paradigm Shift

It can be mentioned that the concept of on-chip interconnection network (NoC) is borrowed from off-chip interconnection networks. Various NoC topologies such as the on-chip communication or interconnection networks are studied for a stable foundation of design approaches.

Research on NoC Architectures

A NoC has therefore emerged as a revolutionary scalable communication mechanism instead and serves as a viable solution over the SoC communication bottleneck [11,12]. The job of the NoC simulators such as Noxim [22] is to replicate similar behavior seen in the actual NoC.

Necessity of NoC Channel Testing

NoC testing is divided into three phases: IP core testing, router testing, and channel testing. Therefore, it is necessary to ensure the correctness of the channels before performing the test for IP cores and routers.

Literature Review

Defect coverage metric – The test engine should achieve a high defect coverage value that can be as high as 100%. Scalability of the method – The scope of a test scheme should not be limited to a particular topology, network size and channel width.

Research Overview

Motivation and Problem Formulation

The advantage of using BIST structures is that they reduce the load on the test area by running a small set of tests. By taking advantage of this advantage, the test algorithm can be run simultaneously on multiple nodes to achieve the goal of reducing the total test time to failure.

Major Contributions of the Thesis

The proposed test algorithm is implemented using a special machine called built-in-self-test (BIST) structure. By testing channel-open errors, the proposed test algorithm addresses both partial and full packet loss caused by the errors in the network.

Organization of the Thesis

This work proposes a time-independent scheme for the analysis of short faults in NoC channels. Optimal On-Chip Co-existing Channel Fault Detection and Diagnosis This work focuses on the detection of production channel co-existing faults in NoC-based systems.


Detailed literature and pros and cons of the state of the art mechanisms for testing communication channels in NoCs are discussed in Section 2.6 and Section 2.7, respectively. Motivation and the list of contributions, which are the basis of the rest of the chapters of this thesis, are mentioned in section 2.8.

NoC Basics

Hard IP cores are physical manifestations of the IP design and synthesized blocks that can be fabricated and placed in the FPGA. The IP cores are the basic message generation centers in the NoC and are supported with buffers.

NoC Topology

The direct topology offers the advantage that the total communication bandwidth increases in the network while the number of nodes increases. Routers in the irregular topologies may show different connectivity patterns depending on the application specification.

Fault Modeling

The SSA fault model is one of the most popular fault models and facilitates test suite generation for a system. In other words, structural testing depends on the specific circuit structure including gate types, interconnects, fault patterns, etc.

Testing of NoC Faults

During the life of the NoC, in the design (pre-manufacturing) and on-design (post-manufacturing) phases, the NoC architecture undergoes the offline testing. Reusing a NoC as a TAM is seen as a cost-effective strategy for testing IP cores embedded in the NoC.

Literature Review: Test of Communication Channels

Note that unlike the replacement/recovery scheme, the fault-tolerant approach "allows faults to be accommodated" in the communication channels of NoC architectures. The test mechanism involved in the detection of transient faults in channels must distinguish these faults from manufacturing faults.


Issues Related to Prior Works

It is noted in the literature that no work has considered open fault testing in NoC channels. Due to the multi-hop transmission of the test data, many errors in the area go unnoticed.

Motivation and Contribution

Two new test scheduling schemes are proposed to lower the overall test time required by the test solution for channel sticking faults in the NoC. A cluster-based test scheduling scheme is proposed to reduce the test time and related performance overhead.


Fifth Contribution – The short and stuck faults assumed to co-exist in the NoC channels are tested by proposing a suitable test method. The co-existing nature of the faults prevents the test algorithm from detecting all short and stuck faults that occur in the channels.


The scalability of the solution and the portability of the proposed scheme are presented successively in Sections 3.7 and 3.8. The various advantages arising from the proposed model over a set of existing approaches are assessed in Section 3.9.

Motivation and Contributions

The proposed test algorithm, called here the “1-step” algorithm, detects both stuck-at-0 (SA0) and stuck-at-1 (SA1) faults on the switch and local channel wires from the node (router and its core). The simulation results reveal a deep insight into the impact of SAFs on NoC performance to demonstrate the online evaluation of the proposed solution.

SAFs and System Level Failures

This failure mode results from the incorrect behavior of a control channel wire carrying the packet header. This packet mishandover is realized as mishandover error during NoC performance evaluation. c) Packet drop-.

Proposed Test Model

At the same time, the router-TPG multicasts the test packets on the shared channels with its connected core and the routers of the neighboring nodes. Therefore, channel wires are kept filled with a packet test vector.

Test Scheduling

The second component is the time required to organize the test set into a test package. The test iterations control the Tn/w, the time required to complete testing the channels on a network.

Experimental Results

The proposed test schedule is applied to test a series of channels and evaluate the test time required to complete testing the SAFs on the NoC communication channels. So the test time required for a channel is the same for all outgoing channels of the node.

Solution Scalability

The same size packets shown in Figure 3.12a are sent on the network for both test rounds. The amount of packets injected into the network is shown in Figure 3.14a, while the amount of received and dropped flights are shown in Figures 3.14b and 3.14c respectively.

Solution Portability

In Figure 3.20 it is seen that the proposed test mechanism is applied four times to the octagon network. The effect of channel SAFs at system level is realized in terms of channel errors and Figure 3.11 can be referred for the errors caused due to SAFs on DWs, CWs and HWs.

Benefits over Prior Works

An improvement in test time for the proposed D-model over the previous models on these networks is given in Table 3.21. Thus, the variation of the D-model becomes 4x faster in terms of test iterations that store test clocks up to on the octagonal network.


In online mode, several incoming application packets must wait on a node that is currently busy testing its channels, and the arbitrator does not release packets on the channels until the node exits the ongoing test mode. Performance Loss: This test time has a significant impact on network performance while the NoC component is in online test mode, causing a performance load that may include latency, power consumption, etc.


Subsequently, the test time is increased by increasing the test repetitions as defined in Equation 3.17. Therefore, despite the fact that it is favorable for many works, the proposed test model needs to be improved by reducing the number of test iterations due to the rapid detection of channel faults and the improvement of network performance degradation.


This chapter exclusively addresses these issues via testing the on-chip communication channels for open faults. Proposed test mechanism followed by convenient test planning is discussed in Section 4.4 and Section 4.5 respectively.


Multiple advantages of the proposed model over the existing models in the form of detailed comparative study are analyzed in Section 4.9. The literature states that most of the fault tolerant approaches do not address a testing mechanism for channel faults [6].

Motivation, Problem Formulation, and Contributions

Simulations using a cycle-accurate simulator are conducted to demonstrate the online evaluation of the proposed test solution with respect to these common performance metrics. Establishing the scalable property of the proposed solution on a network independent of its size and channel width.

At-Speed Test Mechanism

It is found that most of the open faults belong to the intermediate gate type. First, a sufficient sample of A1 is placed in the payload flit of the test packet for the DW channel.

Test Scheduling

The corner nodes in the network (either a P×Q network or . network with N nodes) are selected from its matrix representation as shown previously. In the presence of channels of the same type, the test packet can be routed simultaneously from a single test source (router-TPG) to multiple test destinations (TRA in neighboring routers and ART in its own core).

Simulation Results

The evaluation of the test time that the proposed test algorithm takes on a test iteration depends on the open fault operations of the TM blocks. Similarly, handshake information for the test package should be accommodated with the additional A1 sequence from which to simulate open faults in the HWs.

Solution Scalability

Since the number of channels under test in one iteration is equal as seen in the previous section, the LCM of 32-bit4×4 and other networks remains the same as shown in Figure 4.10. The iterative execution of the testing algorithm by the corner nodes in this network is shown in Figure 4.16.

Solution Portability

It is seen that the network receives up to 90% of the injected traffic when in normal mode. Next, Figure 4.20 illustrates the 4-corner forest on the execution of the proposed test mechanism for the corner nodes in the octagon network.

Comparison Study

For example, the 2×2 model in the online mode selects one 2×2 subnet at a time in the test mode. Few packets are dropped in the network because of the delay the router incurs in processing the packets.



Furthermore, this principle makes the proposed test scheme scalable with respect to the general networks. The proposed test scheme offers a relatively lower number of test iterations, but like the previous works, this number depends on the size of the on-chip networks.


Unfortunately, most of the fault-tolerant approaches do not include a test scheme for detecting channel faults in NoCs. Different system-level error modes caused by the channel short errors are described in Section 5.4.

Motivation, Problem Formulation, and Contributions

Evaluating the proposed solution against hardware domain load, test time, connectivity and fault coverage metrics. Examining the effect of short faults in terms of various well-known performance metrics under significant traffic.

Cluster Formation


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