Technology Computer Aided Design (TCAD) simulations can help overcome all these problems in the best possible way, provided it provides reliable and accurate results. The solution accuracy of the TCAD simulations mainly depends on two main factors; 1) Transport model used for the analysis, and 2) Numerical solution of the transport model, which basically depends on the type of discretization scheme used for the approximation. The method used for circuit analysis with ANN-based semiconductor devices can be easily parallelized, enabling fast solution selection.
Introduction
Several discretization schemes such as finite difference method (FDM), finite element method (FEM), finite volume method (FVM) have been presented in the literature for the analysis of semiconductor devices. In addition, the electrical analogy of various partial differential equations representing the behavior of semiconductor devices [25–28] prompted us to introduce the use of random walk in the analysis of semiconductor devices.
Thesis Motivation and Objective
It is only because of the use of TCAD that we have been able to make such a huge leap in technology in such a short span of time, and so to keep up with this pace we have to depend on highly accurate TCAD tools which you can find solutions for a particular device efficiently. Application of machine learning and random walk method to improve the initial guess of the solution.
Thesis Contributions
In order to achieve these goals, below are the main objectives that must be achieved. Improvise the solution provided by FEM using different stabilization methods, such as DG-FEM and SUPG.
Thesis Organization
Fundamentals of TCAD in Semiconductor Device Analysis
Implementation of FEM and its Variants for Device Analysis
An Accurate and Adaptive Framework based on EFG Method
Random Walk and Machine Learning Algorithms based Analysis of Semiconductor Devices
Conclusion and Future Aspects
Introduction
The critical role of TCAD in the semiconductor device fabrication process can be realized using Figure 2.1. Figure 2.2 shows that the steps involved in developing a device are time consuming and irreversible.
Physical Models for Device Analysis
- Drift-Diffusion Model
- Mesh Formation
- Boundary Conditions
The popular drift-diffusion current equations can be easily derived by applying the Boltzmann transport (BTE) equation by considering moments of the BTE [41]. In the Neumann boundary condition, the gradient of the unknown function is exactly known rather than the function itself and can be represented by equation 2.5.
![Figure 2.3: Shows the hierarchy of various transport models [1]](https://thumb-ap.123doks.com/thumbv2/azpdfnet/10344222.0/42.892.55.775.374.1112/figure-shows-hierarchy-various-transport-models.webp)
A Survey of Different Discretization Methods to Implement Transport Models
Due to the absence of finite elements in the discretization process or its independence from mesh generation, it is called the elementless method. Two different shape functions, moving least squares (MLS) and radial point interpolation method (RPIM), are used in the proposed work to implement the EFG method, which are described in Chapter 4.
Formulation of Basic Device Equations
The built-in potential barrier, Vbi of a PN junction can be described in terms of quasi-Fermi levels as, . Using the above equations for carrier concentration, the built-in potential, Vbi, can be calculated as fermi level, respectively; EF nandEF approach the quasi-Fermi energy levels corresponding to electrons and holes respectively;.
Numerical Solution of Linear Algebraic Equations
Summary
This chapter presents a detailed description of the native TCAD VEDA (Very Efficient Device Analyzer) framework for accurate analysis of semiconductor devices, which includes the Finite Element Method (FEM) and its variants. Discontinuous-Galerkin FEM (DG-FEM) and Streamline upwind Petrov Galerkin FEM (SUPG-FEM) are FEM variants discussed in detail in this chapter to improve the accuracy of the solution. The effectiveness of the proposed methods is confirmed by analyzing various semiconductor devices such as PN junction diode, MOS capacitor and MOSFET.
The simulation results of these devices are compared with a commercially available TCAD simulator, Sentaurus, to verify the correctness of the proposed simulator.
TCAD Framework using Finite-Element Discretization
- Step-by-Step FEM Formulation of a Second Order 1D PDE
- Computational Analysis of FEM
- Implementation Details and Simulation Results
- MOSFET
The 1D PDE for the given case is considered, which is represented by Equation 3.16, and its weak formulation can be defined by Equation 3.17. Now you can calculate each individual expression one by one using the steps below. It can be seen that the final FEM result depends on the number of finite elements considered for a given geometry and the choice of the basis function or its degrees of freedom at each individual element.
A general form of the matrix formulated in the FEM discretization process can be presented with TH.
TCAD Framework VEDA using DG-FEM
- Implementation Details and Simulation Results
The change in basis functions for FEM and DG-FEM is also shown in Fig. The implementation and simulation results of VEDA using DG-FEM are presented in the next section. The discretization process of DG-FEM is similar to FEM as discussed in previous sections.
The work presented here validates the working principle of the DG-FEM discretization methodology along with its achievements, i.e.
TCAD Framework VEDA using SUPG Stabilization Tech- nique
- Formulation of Drift-Diffusion equation using SUPG method
- Simulation Results
This also implies that the mesh spacing with SUPG can be made coarser to get a better solution. It is observed that the similar solution is produced but with fewer iterations (11 using SUPG compared to 19 in DG-FEM). It is also seen that the amount of maximum error decreases with the increase in the degree of polynomials for Lagrange elements.
With further decrease in mesh size, the normalized error reaches saturation, so that the increase in computation time is more w.r.t.
Quantum Simulations with Schr¨odinger-Poisson Solver
- MOS Capacitor
The aforementioned quantum transport model has been used to analyze a heterostructure and a MOS capacitor with dimensions in the nano regime. The simulation results corresponding to the test heterostructure (GaAs/AlGaAs heterostructure) and the MOS capacitor are presented in the next section. The simulation results presented in this section validate the correctness of our proposed TCAD VEDA framework for modeling carrier transport in the nano-regime.
In the next section, the performance analysis of all the discretization schemes presented in this chapter is presented.
Performance Analysis of Different Discretization Schemes
Summary
Various electrical properties such as potential profile, electric field, and total current density are derived through the analysis, and nano-regime semiconductor devices are also efficiently analyzed. This chapter presents the implementation of a highly accurate and adaptive framework based on the Element-Free Galerkin method for analyzing semiconductor devices. In the EFG method, a set of nodes is spread over the entire domain to formulate algebraic equations representing carrier transport in semiconductor devices without using mesh for domain discretization.
The solution provided by the proposed methodology is compared with other discretization techniques, including the methodology adopted by the commercially available TCAD simulator, Sentaurus[2].
Proposed Implementation of EFG Method for Device Analy- sis
The main difference between FEM and EFG lies in the construction of their shape functions. The results obtained through VEDA validate the effectiveness of the applicability of the meshfree method in the analysis of semiconductor devices. Due to the absence of finite elements in the discretization, it is called the element-free method.
The main advantage of EFG comes only from the deployment of these scattered nodes, where correlation between neighboring nodes is defined by the local support domain, which is discussed briefly in the following section.
Element-Free Galerkin Method
- MLS Approximation
- The Weight Function
Approximate values of field variables calculated as the contribution of xI in the local support domain can be described as. The importance of weight function appears when nodes in the local support domain of x more than monomials in the basis function pT(x). To estimate recI, it is mandatory to have at least two nodes in Ithnode's domain of influence.
The use of MLS approximation and weight function in the formulation of the EFG method for semiconductor devices is presented in the next section.
Application of EFG method for the Analysis of Semiconduc- tor Devices
- Discretization of Poisson Equation
- Discretization of Continuity Equation
Redefining the summation limits in equation 4.44 for the entire problem domain transforms it into the following form. The discretized formulation of the Lagrange multipliers, λ for a given node on the core boundary is obtained by interpolating its nodal values and shape functions, which can be represented as follows. The functional defining the essential boundary condition (ψ = ψ onΓe) can be expressed in an integral form as.
Since in the above equation both δΨ and δΛ are arbitrary, equation 4.61 can be satisfied if and only if.
Parametric Analysis of EFG
Implementation Details and Results
- L 2 -Norm Error Analysis
- Computational Complexity
The result obtained in Figure 4.4 shows that EFG outperforms all other methods in terms of accuracy. Simulations are performed to analyze the performance of the developed framework for a different number of nodes. Figures 4.8 and 4.9 present this study, which states that EFG produces the least normalized error for MLS and RPIM compared to any other discretization method.
The high accuracy of EFG method results in more computation time compared to other discretization schemes.
Summary
The computation time of the EFG method can be further reduced by including different parallelization schemes in the future. In the machine learning based approach, artificial neural networks are used to generate a model to predict the potential profile within a semiconductor device for a given set of parameters. The proposed work is extended to perform circuit analysis with machine learning based semiconductor device models.
The machine learning based circuit analysis engine has a clear advantage of less memory usage compared to look-up table (LUT) based circuit analysis technique.
Proposed TCAD framework using Random Walk Algorithm
- Discretization of PDEs and their Equivalent Electrical Circuit
The nodal expression mentioned above can be represented in the form of its equivalent electrical circuit for a single node and is shown in Fig. For the nodes at the boundaries, their equivalent electrical circuit can be designed using two different boundary conditions shown below. An equivalent electrical circuit for the current equation representing the drift-diffusion model can also be derived in a similar manner.
After discretization, the equivalent electrical circuit is formulated by the above combined current equation and is shown in Fig.
Implementation Details and Simulation Results
- PN Junction Diode
It is observed that the random walk method is at least 5x faster compared to KLU for any domain size. The analysis of PN junction diode using VEDA based on random walk is presented in the next section. Thus, a multi-core processor is an ideal platform for analyzing semiconductor devices using the random walk method.
Initial guesses for the analysis of the PN-junction diode are determined using the random walk method, and the corresponding potential profile inside a diode at thermal equilibrium is shown in Fig.
Proposed TCAD Framework using Machine Learning
- Logistic Regression
- Decision Tree
- Random Forest
- Support Vector Machine (SVM)
- Naive Bayes
- Deep Learning with Artificial Neural Network
Since this method predicts based on the probability, it generates output from 0 to 1, which can be further divided based on a certain threshold. Therefore, this method does not work well for modeling the initial guess of the system for semiconductor device analysis. This method is based on the idea of supervised learning and categorizes data based on certain levels of thresholds.
The only drawback of this method is its simplicity, where it is often outperformed by other well-tuned machine learning algorithms.
Circuit Analysis Using Machine Learning
The DNN-based n-channel MOSFET model is adopted for use in the analysis of electrical circuits. It also verifies the correctness of the DNN-based n-channel MOSFET model developed using characterization data. This particular DNN model for a MOSFET's output characteristics can be used to exploit its benefits for circuit simulation.
The DNN-based n-channel MOSFET (NMOS) model is used to analyze different electrical circuits to confirm their robustness.
Summary
The work presented in this thesis is devoted to the design and development of a fast and accurate framework for the analysis of semiconductor components. Various discretization methods such as the finite difference method (FDM), the finite element method (FEM) and the finite volume method (FVM) are being investigated for the analysis of semiconductor components. It motivates us to include a mesh free variant of FEM, EFG (Element Free Galerkin Method) for the analysis of semiconductor devices.
Cheng, “The interpolating element-free Galerkin (IEFG) method for two-dimensional probabilistic problems,” Engineering Analysis with Boundary Elements, vol.
