An NoC architecture as the on-chip communication network is partitioned into three basic building blocks which are the processing elements commonly known as IP cores, data forwarding routers, and data transmission medium known as on-chip communication channels or links. These components are interconnected in various ways resulting in a topology. The topology plays a major role in the performance evaluation and design cost determination for an NoC. Therefore, selecting an NoC topology is an important task of NoC design that could optimize these factors in addition to dealing with many physical characteristics, such as the length of channel wires, degree of a node, and routing schemes. Designers prefer an NoC topology as an interconnection network that has smaller diameter, smaller node degree, lower average distance between source and destination nodes, more number of communication channels, and so on [64].
Definition 2.4. An NoC topology defines a physical organization of interconnected basic components that would construct a network infrastructure, e.g., mesh, torus, octagon.
Definition 2.5. The term diameter in an NoC topology is the number of hops that returns the maximum shorted distance between two nodes.
Definition 2.6. The average of distances of possible node pairs in an NoC topology defines an average distance on the NoC.
Definition 2.7. The degree of a node in an NoC topology is defined as the number of neighbor nodes connected to the former node.
The performance characteristics of an NoC are often influenced by these parameters. For example, a larger diameter stands for a packet to travel more hops while it intends to reach the destination at the farthest. Similarly, a large average distance incurs higher overall latency while smaller node degree makes designers easy to build a network, i.e., NoC topology [8].
Designers and researchers have come up with a variety of NoC archetype that is broadly classified into two networks: regular and irregular NoCs. The regular category is further
subdivided into direct and indirect classes. Note that each type of NoC interconnection has its own pros and cons.
2.3.1 Regular Topology
In aregular NoC interconnection network, the basic communicating elements (IP core, router, and channel) have a regular architectural configurations. For instance, all routers in a regular topology are identical in terms of the number of I/O ports to neighbor routers and the local IP cores. On every regular topology, there is a predefined pattern that defines the way how communication channels from a router are interconnected with another router and/or IP cores. Regular NoC topologies are usually the typical choice for high-performance chip multiprocessors (CMPs). Many reasons, such as better scalability with network size, topology re-usability whenever needed, and reduced design time include the fact. Regular NoCs are sub-classified into direct and indirect networks.
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Figure 2.7: High level view of NoCs with direct topologies.
2.3.1.1 Direct Topology
In the direct topologies, each node has direct connections via channels to a fixed number of neighbor nodes. The direct topology provides the advantage that the total communication bandwidth increases in the network while the number of nodes increases. However, the connectivity for the large direct network that results in high performance, takes higher energy and area costs. Correspondingly, a tradeoff between the connectivity and cost on the design of a direct network is established. Thus, a fully connected direct network where every node is connected point-to-point (P2P)(Figure 2.7a) to all other nodes in the network, is completely prohibitive. Therefore, most direct networks practiced in general include mesh (Figure 2.7b), ring [84], torus (Figure 2.7c) and folded torus [85], octagon (Figure 2.7d) [86,87], spidergon [88,89], etc. topologies.
Most direct topologies are implemented on the orthogonal arrangement of the NoC basic components, i.e., nodes can be interconnected on a δ-dimensional orthogonal space in the manner that every channel whether local or interswitch shows a displacement in a single direction from a router to another router or IP core or vice versa. Conventionally, δ = 2 is used for an NoC topology. A message in one/multiple packets exchanged between nodes distributed in theδ-dimensional space is done using a routing scheme that moves the packets in one direction at a time. A routing in a direct network is fairly simple to implement.
As seen in the literature, a mesh with δ = 2, i.e., a 2D mesh network is the most commonly used NoC architecture among the direct topologies. The network is also the common preference in commercial and industrial NoC products, e.g., Tilera multicore tiled processor family [90], Intel 80-core Polaris chip [49]. Figure 2.7b shows a4×4mesh NoC. A 2D mesh-based NoC architecture is called chip-level integration of communicating heterogeneous elements (CLICHE) [73]. Every router is connected to the single processor or IP core via the local channel. Furthermore, every internal router is connected to four neighbor routers in four directions- north, east, south, and west via interswitch channels while border and corner routers are similarly connected to three and two neighbor routers, respectively. The area of a mesh network linearly grows during its design with the number of nodes increases.
Additionally, a 2D mesh shows scalability limitations after the certain size. Therefore, the current trend of using a mesh-based interconnection network is expected to change in the near future. Alternatively, the topologies may be the concentrated mesh (C-Mesh) [91] designed on the modifications or optimizations of 2D meshes, the WK-recursive network [92] designed on the basis of radically different connectivity patterns.
2.3.1.2 Indirect Topology
The indirect topologies known as multistage networks are the regular NoCs where identical routers are organized in stages. It means, routers in an indirect topology may or may not
be connected to IP cores. The routers connected to IP cores are called external routers while others that do not have any IP core are called internal routers. The IP cores access the network indirectly via the local channels shared with their base routers. Each external router may be connected with one or more IP cores and the corresponding nodes act as the source/destination of packets and information processing centers. On the other hand, internal routers can only use to receive and forward the packets through the network. A simplest indirect topology is crossbar where two neighbor IP cores are separated by a single router.
One can realize other multistage indirect topologies on just cascading together these small crossbars [17]. Several well known indirect topologies are fat tree [93], butterfly, butterfly fat tree (BFT) [11], extended BFT interconnection (EBFTI) [94], flattened BFT (FBFT) [95], and mesh-of-tree (MoT) [96] networks.
2.3.2 Irregular Topology
The regular NoCs are most suited for general purpose designs. However, there may be a specific application that needs a customized NoC for the communication load or set of applications identified at the design time [97]. In these cases, a mixture of direct and indirect networks with a shared bus is designed. The newly designed topology results in an irregular or ad hoc topology. Shared buses provide low bandwidth while a distance between the source and target nodes in direct/indirect topologies increases with their size. One goal of this new topology is then to increase bandwidth availability as compared to a shared bus. Another goal is the reduction of the distance between nodes as compared to regular networks. Routers in the irregular topologies may show different connection patterns depending on the application specification. Additionally, unnecessary routers and channels are removed during designing an irregular network, for example, reduced mesh. Other noted irregular topologies include Clos, Benes, cluster-based hybrid network [17,98].
Although, regular NoCs are widely and always the first commonplace of selection than an irregular NoC to meet the performance requirements and minimum design cost in most modern CMPs and MPSoCs, there are other factors that may break the regularity assumption at runtime. Two main dominant factors are power management events, and faults that include both permanent and transient faults. Therefore, an NoC must be designed in such a way that the architecture is capable of preserving certain performance and the correct operation in presence of the above runtime events [18].