**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

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**COURSE CONTENTS: **

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

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5. Demonstrate an understanding of working principle of operation of different types of memories
6. Demonstrate an understanding of working principles of clocking, power reduction and distribution
**Pre-requisite:**** **Basic knowledge of digital logic design, fundamentals of CMOS Inverter.

**Objectives:**** **This course gives the opportunity to the students to learn about the configuration and
simulation of Very Large Scale Integrated Circuits & Systems. The main purpose of this lab course is
to explore various design style of simple and complex Integrated Circuits(IC) near to students. In this
laboratory students are able to understand about models and model parameters of MOSFET amplifier
CMOS Inverter etc. which are suited for IC Technology.

**Course Contents: **

**Unit I**: Familiarization with MOS model parameters in PSPICE software. Simulation of MOS Inverter
with different loads using PSPICE software. Simulation of CMOS Inverter for different parameters K_{n},
Kp as a design variable in PSPICE software. CMOS inverters -static and dynamic characteristics,
CMOS NAND, NOR and XOR Gates, Layout design and simulation. [2 Lab Sessions]

**Unit-II :** Simulate half-adder, full adder, half substractor, full-sunstractor following behavioral and
structural modeling using VHDL\Verilog. Design of a 4-bit Multiplexer/demultiplexer using
VHDL\Verilog. [4 Lab sessions]

**Unit-III : **Design Flip-Flops, latches, registers, counters, FIR & IIR filters using VHDL/Verilog and
their hardware implementation on FPGA board.[5 Lab sessions]

**Unit-IV:** Implementation and Simulation of 2D/3D PN Junction Diode. Implementation and
Simulation of 2D/3D NPN & PNP BJT. [1 Lab sessions]

**Text/reference Books: **

1. Jan M Rabaey, Digital Integrated Circuits, 2nd Edition, Pearson Education 2. Sung-Mo Kang, CMOS Digital Integrated Circuits, 3rd Edition, McGraw-Hill

3. Pedroni, Volnei A., Circuit Design and Simulation with VHDL, 2nd Edition, MIT Press

4. R. Jacob Baker , Harry W. Li , David E. Boyce CMOS (Circuit Design, Layout, and Simulation) Prentice-Hall of India Private Ltd.

5. J. Bhasker “A VHDL Primer” 3rd Edition, Pearson

6. S. M. Sze& Kwok K. Ng., Physics of Semiconductor devices, Wiley

7. M. Lundstrom& Jing Guo, Nano-scale transistors: Device Physics Modelling and Simulation, Springer

**Outcomes****: **Upon successful completion of this course, students should be able to:

1. Understand the concepts of digital system design methods through practical domain. Design combinational and sequential circuits.

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

59 2. Analyse and layout design of CMOS circuits in micron and submicron level using any platform.

3. Learn techniques and engineering tools (such as HDL, Xilinx / Altera) to design, implement.

**EC65103 Antenna and Wave Propagation ** **L-T-P: 3-0-0; Credit : 03 **
**Prerequisites****: **i) Electromagnetic Field Theory

* Objective: *This course is intended to provide students with a good understanding of the general
characteristics of different antennas, the principles and theory behind their operation, and modelling
techniques for different antenna systems. In addition, the principles and characteristics of radio waves
propagating in various environments and wireless channels are dealt with.

**COURSE CONTENT : **

**Unit I: Introduction: **Introduction to Antennas; Coordinate System, Solid Angle; Fundamental
Parameters of Antennas; Equivalent Circuit of Transmitting and Receiving Antennas. **(4 L)**

**Unit II: Wire Antenna and Radiation : **Radiation: Potential Functions and electromagnetic-field,
alternating current element, power radiated by the alternating current element and radiation resistance,
application to short antennas, radiation from a quarter wave mono pole and Half wave dipole. Antenna

terminologies, Terminal impedances, Mutual impedance of antennas.

**(11 L)**

**Unit III: Different types of Antennas and Arrays : **Yagi-Uda, Log-periodic, Rhombic, Travelling
wave antenna, Horn, parabolic reflector and its fading techniques. Slot antenna, loops, Helical, lens,
Micro strip antenna. Directional properties of dipole antenna, Two element array, three element array,

linear arrays, multiplication of patterns, Binomial array. Radar cross section.

**Unit IV: Propagation of electromagnetic waves : **Various paths of propagation, Space wave and
surface wave, wave tilt of surface wave, spherical earth propagation. Tropospheric wave propagation,
Duct and super refraction. Ionospheric wave propagation& mechanism of reflection and refraction,
critical frequency, MUF, virtual height, skip distance, OWF. Effect of earth magnetic field. Friis

Transmission Formula and Path Loss, Fading ** ** **(12 L) **

**Book List **

1. E. C. Jordan and K. G. Balmain, Electromagnetic Waves and Radiating Systems, 2nd Edition.

Prentice Hall India, India, 2000.

2. John D. Kraus and Ronald J. Marhefka, Antennas for All Applications, 3rd Ed. Tata McGraw Hill, New Delhi, India, 2003.

3. C. A. Balanis, Antenna Theory - Analysis and Design. John Wiley and Sons, Inc, India, 2005.

(Textbook for Antenna)

4. R.E. Collin, Antennas and Radiowave Propagation. McGraw-Hill, 1985.

* Course Outcome: *Upon successful completion of this course, students should be able to:

1. Describe and analyze some simple radiating systems.

2. Analyze basic antenna arrays.

3. Describe and analyze the general characteristics of different types of wire antennas and aperture antennas.

4. Analyze and model the ionospheric, tropospheric, surface wave, and ground wave propagation.

5. Analyze and model the propagation mechanism of modern mobile communication.

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

60

**EC75102 ** **Analog Integrated Circuits **

**L-T-P: 3-0-2; Cr: 04**

**Pre-requisite:**** **Analog Electronics

* Objectives: *To acquaint the students with basic CMOS analog building blocks and analog
sub-system design.

**S. No Contents ** **Contact Hours **

1 Necessity and advantages of CMOS Analog Circuits; review of MOSFETs;

their characteristics and models; components available in MOS technology:

MOS capacitor.

6

2 Overview of MOS amplifiers and their analysis; analysis of typical MOS circuits using square law; frequency response, bandwidth enhancement;

MOS bias circuits; various types of current mirrors (Simple, Wilson, modified Wilson and cascode); differential amp: linear range; diff amp with active load biased with current source: Gm, Rout; Diff. To single ended converter; output stage and level shifting stage.

10

3 Op-amp architectures: CMOS op-amps; two stage CMOS op-amp architectures; calculation of overall gain and rout; determination of dominants poles; compensation and relocation of poles and zeros; other CMOS op-amp architectures. Gilbert cell. High performance CMOS op- amp LNLV op-amp/ Differential op- amp. Stability and frequency compensation, multipole systems, Phase margin.

8

4 CMOS OTAs and transconductors: CMOS OTA-linear range and transconductance; linearized CMOS OTSs-single ended and differential.

8

5 MOSFET-C integrated filters; MOS fully differential integrator, derivation of MOSFET-C biquads based on conventional op-amp RC biquads.

Nonlinearity cancellation in MOS Analog Circuits: basic topologies for non-linearity cancellation using one, two and four matched MOSFETs;

exemplary circuits for realising linear grounded / floating CMOS voltage- controlled oscillators. Introduction to MOS translinear and square root domain circuits.

10

**TOTAL ** **42 **

**Lab Experiments: **

1. Study of MOS I-V and C-V characteristics 2. Lambda and FT calculation for PMOS & NMOS

3. Design and simulation of Single Stage Amplifier and transconductance plot 4. Design and simulation of Common Source Amplifier

5. Design and Simulation of Common Gate Amplifier 6. Design and simulation of Common Drain Amplifier

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

61 7. Design and simulation of Single Stage Amplifier with different load

8. Implementation and study of Current Mirror Circuits 9. Design and simulation of Differential Amplifier

10. Design and simulation of Folded Cascode Operational Amplifier 11. Design and simulation of Two stage Operational Amplifier

12. Implementation and study of Operational Transconductance Amplifier (OTA)
**Suggested Books : **

**Text Books : **

1. Behzad Razavi, Design of Analog CMOS integrated circuits, McGraw Hill Co. Inc.

2013
2. R. Jacob Baker, CMOS: circuit Design, Layout and Simulation, Wiley 2009
**Reference Books : **

1. Douglas R. Holberg, Phillip E. Allen, CMOS Analog Design, 3rd Edition,

Oxford University Press

2013 2. Paul R. Gray , Paul J. Hurst , Stephen H. Lewis , Robert G. Meyer

Analysis and Design of Analog Integrated Circuits, 5th Edition, Wiley

2009 3. Mohammed Ismail and Terri Fiez, Analog VLSI: Signal and

Information Processing, McGraw-Hill

1994 4. Geiger, Allen and Stradder, VLSI Design Techniques for Analog and

Digital Circuits, Tata McGraw-Hill Education

2010 5. David A johns, Ken Martin, Analog Integrated Circuit Design, Wiley 2008 6. R. Gregorian and G.C Ternes, Analog MOS Integrated Circuits for

Signal Processing, Wiley

1986 7. Roubik Gregorian, Introduction to CMOS OpAmp and Comparators,

Wiley

1999 8. Alan Hastlings, The art of Analog Layout, Wiley 2005 9. Relevant research paper from specific area

**Course Outcomes: **Upon successful completion of this course, students would be able to:

CO1: Understand the basic mode of operation of MOS capacitor and construct MOSFET CO2: Analyze the operation of MOS amplifiers

CO3: Understand the design of operational amplifier using MOS and study the compensation techniques

CO4: Design Operational transconductance amplifiers (OTA) and study OTA for different applications

CO5: Design and analyze MOSFET-C Integrated filters and voltage-controlled oscillators

**EC75103 ** **MOS Device Physics and Modelling ** **L-T-P: 3-0-2; Cr: 04 **

**Pre-requisite:**** **Basic knowledge in Semiconductor Physics/Devices.

* Objectives:* The course will provide adequate understanding of semiconductor devices and their
modeling aspects, useful for designing devices in electronic, and optoelectronic applications.

**Sl. **

**No. **

**Contents ** **Contact **

**Hours **

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

62 1 Energy Band Diagram (E-K) of Silicon, Concept of effective mass, Fermi and

quasi-Fermi levels, Carrier Transport. MOS Capacitor:** **Energy band diagram of
Metal-Oxide-Semiconductor contacts, Mode of Operations: Accumulation,
Depletion, and Inversion, 1D Electrostatics of MOS, Depletion Approximation,
CV characteristics of MOS, LFCV and HFCV.** **

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2** ** Basic physics of MOS transistors scaling, charge sharing effect (CSE), narrow
and reverse narrow width effect, SCE, DIBL, GIDL, mobility degradation due to
gate field, hot electron effect and velocity saturation, channel in-homogeneity,
velocity overshoot, tunneling through oxide.

8 3 SOI MOSFET: FDSOI and PDSOI, 1D Electrostatics of FDSOI MOS, VT

definitions, Back gate coupling and body effect parameter, IV characteristics of FDSOI-FET, FDSOI-sub-threshold slope, Floating body effect. Advanced MOSFETs

6

4 IV Modelling: Gradual Channel Approximation, Sub-threshold current and slope, Body effect, Detail 2D effects in MOSFET, High field and doping dependent mobility models, High field effects and MOSFET reliability issues (SILC, TDDB,

& NBTI). Large Signal and Small Signal Modelling of MOSFETs

6

4** ** Non-idealities in MOS, oxide fixed charges, interfacial charges, Mid-gap gate
Electrode, Poly-Silicon contact, inversion layer quantization, quantum

capacitance. 6

5 Leakage mechanisms in thin gate oxide, High-K-Metal Gate MOSFET devices
and technology issues, MOSFET capacitances and resistances, properties of
junction and Ohmic and Schottky contact, tunneling, fowler-Nordheim tunneling,
direct tunneling** **

6

**42 **
**Suggested Books : **

**Text Books : **

1. S.M. Sze & Kwok K. Ng, Physics of Semiconductor Devices, Wiley 2007 2. Yuan Taur & Tak H. Ning, Fundamentals of Modern VLSI Devices, Cambridge

2013 3. Mark Lundstrom & Jing Guo, Nanoscale Transistors: Device Physics, Modeling

& Simulation, Springer 2006

**Reference Books : **

1. Yannis Tsividis, Operation and Modeling of the MOS Transistor, Oxford

University Press 2010

2. J. P. Colinge “FinFET and other multi-gate transistors” Springer 2008 3. Research papers from specific area

**Lab Experiments: **

1. Implementation and Simulation of 2D-PN Junction Diode.

2. Implementation and Simulation of 3D-PN Junction Diode.

3. Implementation and Simulation of 2D MOS Capacitor: CV characteristics.

4. Analysis of non-idealities in MOSCAP.

5. Implementation and Simulation of 2D/3D NPN BJT.

6. Implementation and Simulation of 2D/3D PNP BJT.

7. Implementation and Simulation of PD-SOI MOSFET.

8. Implementation and Simulation of FD-SOI MOSFET.

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

63 9. Simulation of 2D/3D NMOSFET Channel Length 20nm or higher.

10. Basic electrical performance parameters extraction of MOSFET.

11. Implementation and Simulation of ohmic and rectifying contacts.

12. Implementation and Simulation of some emerging devices: FINFET, JLFET.

* Outcomes:* After completion of course, students would be able to explain the modeling aspects and
physics of semiconductor, E-k diagram and Fermi energy level, leakage mechanism in gate oxide of
devices, junction effect, tunneling and scaling in MOS.

CO1 Understand the basic structure and principle of semiconductor materials, and construct semiconductor diode

CO2 Evaluate the electrical performance parameter of semiconductor PN junction diode.

CO3 Design MOSFET and estimate their electrical performance parameters.

CO4 Study the different types of Metal-semiconductor contacts: Ohmic and Schottky contact.

CO5 Understand the impact of energy band diagrams of different device.

CO6 Use software based experiments to demonstrate various aspects of different device structures.

CO7 Recognize the necessity of life-long learning through timely exposure to the evolving and new technologies in the field of semiconductor devices.

**EC85102 ** **Digital Integrated Circuits ** **L-T-P: 3-0-2; Cr: 04 **

** **

**Pre-requisite:**** **Knowledge of Digital Circuits.

* Objectives: *To acquaint the students with the fundamental concepts of digital VLSI circuit
design in order to optimize the digital building blocks at circuit level.

**S. No Contents ** **Contact **

**Hours **
1 Review of MOSFET operation and CMOS process flow, Layout and design

rules, Design Hierarchy, Concepts of Regularity, Modularity and Locality,
VLSI Design Styles, VLSI Design Flow, Computer-Aided Design Technology.** **

5

2 CMOS inverter: Static characteristics, Resistive Load Inverter, n-type MOSFET Load, CMOS Inverter, Dynamic Characteristics and Interconnect Effects, Calculations of delay, Inverter Design with Delay Constraints, Estimation of Interconnect Parasites, RC model for interconnects, transmission lines, Switching power dissipation of CMOS inverter.

7

3 Combinational logic: Transistor sizing in static CMOS logic gates, static CMOS logic gate sizing considering method of logical effort, dynamic logic, pass- transistor logic, common mode and other cross- coupled logic families.

6

4 Sequential logic: Static latches and flip-flops (FFs), dynamic latches and FFs,
sense-amplifier based FFs, Advance logic circuit design, Schmitt trigger,
Monostable and Astable circuits. Advanced Techniques in CMOS logic circuit**: **

Pseudo nMOS, Tri-state, Clocked CMOS, Dynamic CMOS logic- Domino, NORA, Zipper.

8

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

64 5 Memories and array structures: MOS-ROM, EPROM, EEPROM and flash

memory, SRAM/DRAM cell, memory peripheral circuits, signal to noise ratio, power dissipation, Low power memory design techniques.

8

6 Timing issues: Timing fundamentals, clock distribution, jitter, self- timed circuit design, Digital Phase Locked Loop, Adders, Multipliers and Shifters.

8

TOTAL 42

**Lab Experiment: **

1. Introduction to SPICE Circuit Simulator.

2. Realization of NOR Gate Using RTL Logic. Obtain & Plot its Transfer Characteristics And Determine Noise Margins, Fan-Out and Propagation Delay.

3. Realization of NAND Gate Using TTL Logic. Obtain & Plot Its Transfer Characteristic and Determine Noise margins, Fan-out and Propagation Delay.

4. Realization of Wired NAND Gate Using DTL and MDTL Logic. Obtain & Plot Its Transfer Characteristic and Determine Noise margins, Fan-out and Propagation Delay.

5. Implementation of NMOS Inverter, Obtain & Plot Its Transfer Characteristics and determine Noise margins And Measure Propagation Delay.

6. Implementation of CMOS Inverter. Obtain & Plot Its Transfer Characteristics, Determine Noise Margins and Measure Propagation Delay.

7. Realization of MOSFET Characteristics Using Circuit Simulator Characteristics and BSIM Models.

8. Realization of Inverter Gate Using BiCMOS Logic, Obtain & Plot Its Transfer Characteristics, Determine Noise Margins.

9. Realization of CMOS Static & Dynamic Characteristics Using Circuit Simulator Characteristics and BSIM Models.

10. Design and Implementation of TTL-CMOS & CMOS-TTL Interfacing.

11. Design and Implement of 1-Bit RAM CELL Using JK & SR Flip-Flop.

12. Layout of CMOS Inverter and Parasitic Extraction and Obtain VTC of Extracted Net List.

**Suggested Books: **

**Text Books: **

1 Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital

Integrated Circuits: A Design Perspective,” Prentics Hall 2016 2 Sung-Mo Kang, Yusuf Liblebici, “CMOS Digital Integrated Circuits,” Tata

Mc Graw Hill

2003
**Reference Books: **

1 R. Jacob Baker, “CMOS Mixed-Signal Circuit Design,” Wiley India Pvt.

Ltd.

2009 2 Ivan Sutherland, R. Sproull and D. Harris, “Logical Effort: Designing Fast

CMOS Circuits”, Morgan Kaufmann

1999 3 Pedroni, Volnei A., Circuit Design and Simulation with VHDL, 2nd

Edition, MIT Press

2011 4 J. Bhasker “A VHDL Primer” 3rd Edition, Pearson 2015 5 S. M. Sze & Kwok K. Ng., Physics of Semiconductor devices, Wiley 2007 6 M. Lundstrom & Jing Guo, Nano-scale transistors: Device Physics 2006

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

65 Modelling and Simulation, Springer

7 Relevant research papers from specific area

**Course Outcomes**: Upon successful completion of this course, students would be able to

CO1: Understand the basic operation of MOSFET and Design CMOS inverter with layout rules and buffer design using logical effort

CO2: Analyze the performance parameter of Combinational logic circuits CO3: Design Sequential circuits and estimate their performance parameters CO4: Estimate the stability and performance of Memories and array structures

CO5: Identify the timing issues in digital integrated circuits and understand the basic building blocks of Digital subsystem Design.

CO6: Use software-based experiments to demonstrate various aspects of different digital systems.

CO7: Recognize the necessity of life-long learning through timely exposure to the evolving and new technologies in the field of digital systems.

**EC85103 ** **ASIC System Design ** **L-T-P: 3-0-2; Cr: 04 **
**Pre-requisite: **Analysis and Design of Digital Integrated Circuits** **

**Objectives: **Upon completion of this course, students will be able to identify new developments in
SoC design.

**S.No ** **Content ** **Contact **

**hours **
1. Introduction, Types of ASIC’s Design Flow, CMOS Logic,** **ASIC Library

Design, Transistor Parasitic Capacitance, Input Slew Rate, Library-Cell Design, Library Architecture, Programmable ASICs, The Antifuse Metal Antifuse, Static RAM, EPROM and EEPROM Technology, Practical Issues.

10

2. Programmable ASIC Logic Cells, Actel, Xilinx LCA., XC3000 CLB, XC4000 Logic Block, XC5200 Logic Block, Xilinx CLB Analysis, Logic Expanders, Programmable ASIC I/O Cells, Totem-Pole Output, Mixed- Voltage Systems, Metastability, Xilinx I/O Block, Boundary Scan.

8

3. Programmable ASIC Interconnect and Programmable ASIC Design Software, Actel ACT, RC Delay in Antifuse Connections, Xilinx EPLD Logic Synthesis, FPGA Synthesis, Third-party Software, low level design entry, logic synthesis, simulation.

8

4. Programming technologies, commercially available FPGAs, Xilinx’s Vertex and Spartan, Actel’s FPGA, Altera’s FLEX 10k.

8 5. Test and ASIC construction, VHDL, Verilog HDL, Logic Synthesis,

Simulation.

8

Total 42

**List of Experiments: **

1. Design and simulate logic Gates (AND, OR, NAND, NOR, NOT, XOR, XNOR) using gate- level, data flow, and behavioral modeling styles in Verilog HDL.

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

66 2. Design and simulate half adder and full adder using Verilog HDL.

3. Design and simulate full substractor using Verilog HDL.

4. Design and simulate 2:4 Encoder/Decoder using Verilog HDL.

5. Design and simulate 2-bit Comparator using Verilog HDL.

6. Design and simulate D- Flip Flop and J-K Flip Flop using Verilog HDL.

7. Design and simulate Up-Counter using Verilog HDL.

8. Design and simulate SIPO register using Verilog HDL.

9. Design and simulate FIR and IIR filter using Verilog HDL.

10. Do a project based on Verilog HDL.

**Suggested Books: **

**Text Books: **

**1. ** Michel John Sebastian Smith, Application Specific Integrated Circuits,
Addison Wesley Professional

2008
**2. ** Himanshu Bhatnagar, Advanced ASIC Chip Synthesis: Using Synopsys

Design Compiler, 2nd Edition, Kluwer Academic Press** **

2001
**Reference Books:**

**1 ** John V. Old Field, Richrad C. Dorf, Field Programmable Gate Arrays,
Wiley

2001
**2 ** Stephen D. Brown, Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic,

Field Programmable Gate Arrays, 2nd Edition, Springer

1992
**3 ** Relevant research papers from specific area

**Course Outcomes: **Upon successful completion of this course, students would be able to:

CO1: Define and describe digital design flows for system design and recognize the trade-offs involved in different approaches.

CO2: Understand the basic of ASIC and FPGA based system design.

CO3: Understand the design principle and operation of FPGA board and their design techniques.

CO4: Design and analyze ASIC based blocks using HDL language and prototype is validate using Xilinx FPGA board.

CO5: Carry out research and development in the area of ASIC design problems to serve VLSI industries

**Department of Electronics and Communication Engineering **
**National Institute of Technology, Patna. **

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