3.9 Benefits over Prior Works
channels have been tested. The bit-width of a channel is 16-bits. Also, the bit-width of the channel-wire sets (DWs, CWs, HWs) is maintained as mentioned in Section 3.6. Figure 3.10 shows the FCM achievement by applying the proposed test mechanism on a 16-bit channel, can also be used for the octagon network. The size of SA0s and SA1s detected by the test mechanism after a test round is provided in Table 3.18. It shows that all faults have been covered. The effect of channel-SAFs at system-level is realized in terms of channel-errors and Figure 3.11 can be referred for the errors caused due to SAFs on DWs, CWs, and HWs.
To properly evaluate the proposed test mechanism along with graph-color based advanced test scheduling approach (variation of the D-Model) on an octagon network of 16-bit channels, it is needed to carry simulation on the network. The simulation setup using the Noxim 
simulator is extended to the 16-bit octagon network. The performance of the network in on-line mode can be observed in Figure 3.23. Packet flits are injected on the network at the PIR=0.01–0.10 and are provided in Figure 3.23a. The same size of flits is used in each test round. The SAFs whence experienced in a routing path may then infect the injected flits. The infected flits may be corrupted, misrouted, and dropped. The original flits are received with corrupted and misrouted flits in the network. Figure 3.23b shows the size of flits received in the network while the size of dropped flits due to channel-SAFs and timeout error is provided in Figure 3.23c. It is observed that 11–27% and 6–13% of the injected traffic are observed as corrupted and misrouted flits, respectively. Whereas, 7–11% flits are dropped due to SAFs in addition to 8–14% timeout flits. Thus, dropping of flits at last two rounds is comparatively less than first two rounds. It is because of the fact that the size of channels under test in later cases is less (33%) than the former cases. In addition, the later rounds last for the single iteration. The network performance characteristics namely throughput, packet latency, and energy consumption are seen in Figures 3.23d, 3.23e, and 3.23f, consecutively.
Table 3.19: Comparison of Tits vs. Test models..
N/w Size 2x2-Model [38,39] S-Model [6,7] H-Model OE-Model D-Model
2×2 1 8 3 2 3
3×3 4 18 5 2 5
4×4 9 32 7 4 7
5×5 16 50 9 6 9
6×6 25 72 11 10 11
7×7 36 98 13 12 13
8×8 49 128 15 16 15
9×9 64 162 17 20 17
10×10 81 200 19 26 19
11×11 100 242 21 30 21
12×12 121 288 23 36 23
13×13 144 338 25 42 25
14×14 169 392 27 50 27
15×15 196 450 29 56 29
Model) , sequential model (S-Model) [6, 7], hierarchical approach (H-Model) [RPC-18], and odd-even model (OE-Model) [RPC-12, RPC-14] are selected to illustrate the benefits of the proposed test scheme on these prior models in terms of the following quality metrics- hardware area overhead, test time, channel errors, and performance overhead under the similar test environment.
3.9.1 Benefits in Hardware Area Overhead
The test architecture (here a TM) is a crucial component in implementing a test mechanism.
The component should occupy least hardware space and be powerful enough to cover channel- faults. In2×2-Model, basic test configuration consists of a2×2mesh network and is iterated on a larger mesh to cover channel-faults. In the test setup, TM units are placed in core blocks.
Test packets are delivered from a core to another core in the XY routing path. The separation between sender and receiver is thus four hops (2 interswitch and 2 local channel length).
Therefore, handling the test sets, a TM takes a sufficiently higher area and it is ≈ 21–23%
of a router. The test model scales with mesh networks only due to 2×2 test configuration.
However, the test configuration is partially used by the P-2×2-Model to overcome the issue of the 2×2-Model. The area overhead is seen to be 73.84–78.01% more than the proposed TM. In P-2×2-Model, two neighbors TMs separated by three hops (1 interswitch and 2 local channels) exchange test sets to address SAFs. Consequently, little reduction in the area overhead is observed. In S-Model, the SAFs are addressed in interswitch channels only and
Table 3.20: Comparison of Test time (clocks) vs. Test Models.
N/w Size 2x2-Model [38,39] S-Model [6,7] H-Model OE-Model D-Model
2×2 30 88 120 22 33
3×3 120 198 200 22 55
4×4 270 352 280 44 77
5×5 480 550 360 66 99
6×6 750 792 440 110 121
7×7 1080 1078 520 132 143
8×8 1470 1408 600 176 165
9×9 1920 1782 680 220 187
10×10 2430 2200 760 286 209
11×11 3000 2662 840 330 231
12×12 3630 3168 920 396 253
13×13 4320 3718 1000 462 275
14×14 5070 4312 1080 550 297
15×15 5880 4950 1160 616 319
a TM takes 9–12% area. But, local channels are likely to be affected by the faults. The TM block needs additional logic gates to handle sufficient test sets thereby increasing its size to 15–17%. It is still 24.17–31.58% larger than the proposed TM. In H-Model, one channel-wire is taken at a time. Therefore, a TM takes few additional gates yielding 15.89–23.84% more area overhead. The TM blocks used in OE-Model and the proposed D-Model are alike. No benefit is gained in terms of area overhead metric.
3.9.2 Benefits in Test Time
In the on-line mode, a part of an underlying NoC called subnet is kept busy in testing its channels while rest of the network can be used to transmit packets. The selection of suitable subnets determines the number of test rounds which is completed in few test iterations.
Again, these iterations incur the Tn/w, total test time (cost) in addressing the underlying channel-faults. The number of test iterations and corresponding test time (clocks) needed to address channel-SAFs by the prior models on theM×N networks are provided in Tables 3.19 and 3.20, respectively. An improvement in test time of the proposed D-Model over the prior models on these networks is provided in Table 3.21. In2×2-Model, basic test configuration is iterated on largerM×N mesh NoCs resulting(M−1)×(N−1)test rounds. Each round is completed with the single iteration where each test packet from test source is analyzed after traversing four hops. All four routing paths in the 2×2 neighborhood are put to test that takes 30 clocks. Apparently, though the model gains by 3 clocks over the D-Model but its
Table 3.21: Improvement (%) on Test time (clocks) by the proposed D-Model over existing test models.
N/w Size 2x2-Model [38,39] S-Model [6,7] H-Model OE-Model
2×2 – 62.5 72.5 –
3×3 54.17 72.22 72.5 –
4×4 71.48 78.13 72.5 –
5×5 79.38 82 72.5 –
6×6 83.87 84.72 72.5 –
7×7 86.76 86.73 72.5 –
8×8 88.78 88.28 72.5 6.25
9×9 90.26 89.51 72.5 15
10×10 91.4 90.5 72.5 26.92
11×11 92.3 91.32 72.5 30
12×12 93.03 92.01 72.5 36.11
13×13 93.63 92.6 72.5 40.48
14×14 94.14 93.11 72.5 46
15×15 94.57 93.56 72.5 48.21
(2×2-Model) application on a2×2network becomes equivalent to an off-line test application since all channels are put to test. In the place, OE-Model that selects a neighborhood of 16-nodes in a test round may be preferred. The approach then saves 26.67% test clocks. In S-Model, each test round is equivalent to a subnet that consists of a node and its neighbors.
Every round is completed in two iterations. In the first iteration, all outgoing channels while incoming channels of a node in next iteration are tested. Thus, the number of test iterations obtained by this test model on a network of ℵ nodes is 2ℵ. As seen in Table 3.21, the proposed D-Model improves test clocks by 62.50–93.56%. Although, the H-Model and the D-Model has addressed channel-SAFs on the same number of test iterations, yet the later model saves 72.50% test clocks over the former model because its test mechanism applies every test bit from the test sets serially. Apparently, the OE-Model takes fewer test clocks over the D-Model for the networks up to 7×7 dimensions. On the contrary, application of the OE-Model on smaller networks (of size up to 4×4) has no longer remained in the on-line test mode. The reason is that the basic test subnet (test round) in the approach consists of a neighborhood of 16 nodes. Thus, the number of test rounds on a network of ℵ nodes is
≈ dℵ/16e resulting≈ dℵ/8e test iterations. However, for larger networks, the model becomes time-inefficient. The proposed D-Model, for example, improves test clocks by 6.26–48.21% on the8×8−15×15 networks. Therefore, the D-Model becomes faster up to16× in terms of test iterations and save test clocks up to 94.57% over the prior models on a set of networks described in Table 3.12.
The 2×2-Model does not fit on a network other than meshes, for example, octagon network. In the place, P-2×2-Model can be employed where every interswitch channel and its adjacent local channels are put to test in an iteration. Since test packets are analyzed after traveling three hops, the time per iteration becomes 23 clocks. So, the addressing channel- SAFs on a basic octagon NoC take 552 clocks resulting 88.04% more than that of the variant of D-Model. Other test models can also be applied to the octagon network. Subsequently, 176, 200 clocks are taken in this network by the S-Model and H-Model resulting 62.50%, 67%
more test time overhead, respectively than the proposed solution. Note that, the OE-Model though takes only 22 clocks but the test application as mentioned earlier, is no longer in the on-line mode. Thus, the variation of the D-Model becomes4×faster in terms of test iterations that saves test clocks up to 62.50–88.04% on the octagon network.
Figure 3.24: Comparison on payload error vs. Test models on networks of 16-bit channels.
Figure 3.25: Comparison on misrouting error vs. Test models on networks of 16-bit channels.
Figure 3.26: Comparison on timeout error vs. Test models on networks of 16-bit channels.
3.9.3 Benefits in Channel Errors
The manufacturing defects in channels put on-chip communication architectures into different system-level failure modes. Depending on the type of faults experienced in the channels, these
failure modes are observed. For example, the failure modes due to channel-SAFs are described with corruption, misrouting, and dropping of packets. Consecutively, these modes are realized in terms of errors in channels that affect the application packets. The substantiality of the errors that produce infected packets depends on the size of SAFs experienced in channels of a routing path. An NoC architecture should embed a post-manufacturing test mechanism to address these faults. It is necessary for a fault-tolerant routing algorithm that uses the diagnosis results to tackle a faulty channel of a routing path. Furthermore, the number of test rounds, as well as test iterations per round, may bring more infected packets. Because application packets get more chances to enter a test region where channel-SAFs are assumed to exist. Figures 3.24, 3.25, and 3.26 manifest the infected packets due to channel-SAFs as the channel errors. The manifestation is observed by applying a set of test schemes including the proposed D-Model on the 2×2–15×15 networks. For example, when the2×2-Model is applied, 14.78–38.10%, 14.03–18.74%, 18.13–29.57% of the injected packet flits are observed respectively as payload, misrouting, and timeout errors which are noticeably more than as observed by the proposed D-Model.
Figure 3.27: Improvement (%) on packet latency by the proposed D-Model over existing test models.
Figure 3.28: Improvement (%) on energy consumption by the proposed D-Model over existing test models.
3.9.4 Benefits in Performance Overhead
The effects of channel-SAFs are realized in the shape of errors which significantly affect the performance characteristics of NoC-based communication systems. Simultaneously, the effects become more evident with the number of test iterations along with other routing constraints. Higher is the number or more is the test time taken in an iteration, worse is the NoC performance degradation/overhead. Here, the performance characteristics in terms of packet latency and energy consumption are observed by conducting system simulations.
The simulations are done to evaluate the prior test solutions on the networks characterized in Table 3.12. As a result, one may be acknowledged of the superiority of the proposed solution
over the prior approaches. Figure 3.27 refers the packet latency degradation of the prior models over the D-Model. In the on-line mode, multiple incoming application packets have to wait at a node currently busy in testing its channels and the arbiter unit does not release the packets on the channels until the node has left the ongoing test mode. As a result, the latency of a packet is increased. For example, when the 2×2-Model is applied on a 2×2 network, packet latency on average is 15.11% more and the parameter degrades to 33.19%
whence the model is applied to the 15×15 network. Likely, sequencing the simulations by the S-Model, H-Model, and OE-Model on the network sizes ranging from2×2–15×15, one may expect, respectively 16.22–40.40%, 10.12–18.89%, and 5.43–13.26% more packet latency.
The deterioration in energy consumption for the prior methods is shown in Figure 3.28. As mentioned, applications duly wait at a node before forwarding on a channel till its testing is over. In this period, network resources are utilized to hold the packets at the node as well as preceding packets on the routing path. The energy consumed by a packet flit is just like the latency is increased. For example, 10.03% and 33.53% more energy are consumed by an application of the 2×2-Model on 2×2 and 15×15 networks, respectively. Subsequently, applying the S-Model, H-Model, and OE-Model on the set of2×2–15×15networks, it can be observed that the proposed D-Model consumes 13.57–46.52%, 12.26–19.68%, and 6.41–10.90%
energy less than those prior models.