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LOW POWER ANALOG VLSI DESIGN WITH ADVANCED COMPACT MOSFET MODEL

BY

AMEETA CHIMULKER

Submitted

In fulfiffment of the requirements of the degree of Doctor of Thirosophy

537

GN I/ Low

T-110

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CERTIFICATE

Certified that the work incorporated in the thesis "LOW POWER ANALOG VLSI DESIGN WITH ADVANCED COMPACT MOSFET MODEL" submitted by Ameeta Chimulker, was carried out by her under our supervision and the work included in this thesis has not been submitted / utilized for any other degree. Such material as has been obtained from other sources has been acknowledged in this thesis.

( LIBRA

Prof. A.B. Bhattacharyya (Guide)

ce m yzect

.5)-(cfgati

c c;;3/41

1/1_0q

4

:d-ekol,-Z

L et /

Pr a A NI- G doylcAy

Gz7, g"- 0

8"

Prof. .A.E..Desa (Co-guide)

Head, Department of Physics

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ACKNOWLEDGEMENT

I acknowledge with great pleasure the contribution of my guide Prof.A.B.Bhattacharyya for his support in my official commitments and providing moral support in times of distress. His support, encouragement and occasional goading have helped me see a research problem in the right perspective and look for solutions in the right directions, I am thankful to him for creating in me a better awareness to the technical and also the non-technical aspects of research, and for inspiring me to think in the proper direction. I consider it a great privilege to have worked with him.

I also acknowledge the co-operation and help from my co-guide Prof. J. A. E. . Desa and the staff at the VLSI Design Centre in the Physics Department of Goa University, and the many friends in the Department.

I also thank Prof P. R. Sarode of Physics Department, Goa University, for providing me the facilities for this research work.

(4)

1

ABSTRACT

The work presented in the thesis evolves around the following ideas:

1. Development of a small signal MOSFET model considering second order effects and valid for all levels of inversion (strong, moderate and weak).

2. Comparison of performance of single transistor amplifier configuration for different inversion levels and determination of optimum inversion level for maximum gain for a given ft.

3. Development of design guidelines for a 2-stage CMOS operational amplifier to meet certain specifications without any design iterations and valid for all levels of inversion.

Study of mismatch errors for the standard current mirror configurations at all inversion levels.

5. Development of scaling rule for MOSFET with reduction in power consumption and its application to an operational amplifier design.

The thesis has been organized in 7 chapters, contents of which are briefly given below.

(i)

Chapter-1 introduces the rationale of investigating low-power CMOS analog design at different inversion levels. Motivation and need of development study of the analog blocks viz MOS amplifier, operational amplifier and current mirror are justified.

(5)

(ii) Chapter-2 describes the rtc mngPFT model considering second order effects. The second order effects such as CLM, DIBL, velocity saturation are represented as different components of the drain , gate and source transconductances and are compared at different inversion levels.

(iii) In Chapter-3 , the the single stage amplifier design is optimized for maximum gain Bandwidth. The common source amplifier is found to give maximum gain at a given ft when operation at an optimum inversion level of 90.

(iv) Chapter-4 gives the details of 2-stage CMOS operational amplifier design.

Analytical expressions using the Advanced Compact Mosfet (ACM) Model valid for all inversion levels are derived for all the

operational amplifier and design guidelines were developed for meeting given specifications of operational amplifier.

(v) Chapter-5 deals with the analysis oft" DC err ors =n currant mirrors

at different inversion levels and its impact on the design.

(vi) The optimum scaling for reduction in power consumption is described in Chapter-6. The scaling laws are applied to single stage amplifier and operational amplifier using the ACM model.

(vii)Finally, conclusions and future scope of work is summarized in Chapter-7.

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LIST OF SYMBOLS

- drain current

Ip - intrinsic current L, e c, equivalent length

transistor width L, transistor length Nip pinchoff voltage

V -ro threshold voltage in equilibrium V. intrinsic source to bulk voltage Vp intrinsic drain to bulk voltage

n slope factor slightly dependent on VG, greater than one and usually less than two. (derivative of gate voltage with respect to pinch-off voltage)

thermal voltage

cl3F fermi potential for holes

it.20 low field mobility

C.. gate oxide capacitance! utTit area IC inversion coefficient

L - transistor length 1■ISI.J13 - channel doping V FB flatband voltage

AL - shrink flA

A - channel length modulation parameter Vcs - drain to source voltage

(7)

UCRIT - longitudinal critical field V/m

9 (THETA)- mobility reduction coefficient due to transversal field y(GAMMA)- body effect factor

a (SIGMA) - DIBL coefficient PHI - bulk Fermi potential VMAX - saturation velocity TOX - oxide thickness

gmdb - drain transconductance gmgb - gate transconductance gmsb - source transconductance VTO - zero bias threshold voltage XJ - Junction depth

LAMBDA - channel length modulation parameter

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LIST OF FIGURES

Fig 2.1 ThP referred MOSFET small signal model

Fig 2.2 Saturation Channel Conductance g mdb and its components at V Ds=3V and V SB=OV

Fig 2.3 Saturation Source Transconductance gmsb and its components at V Ds=3V Fig 2.4 Saturation Gate Transconductance g mgb and its components at V Ds=3V

and VSB=OV

Fig 2.5 Plots of Drain Conductance Sensitivities Fig 2.6 Plots of Source Transconductance Sensitivities Fig 2.7 Schematic Diagram of MOSFET Cascade Stage Fig 2.8 Small Signal Equivalent of Cascade Stage Fig 3 .1 Plot of

adboutio for Afferent inversion levels

Fig 3.2 Plot of attainable DC gain for different channel lengths, obtained analytically and by simulation, with the inversion level (coefficient) or transition frequency as parameter.

Fig 3.3 Schematic Diagram of Common — Source Amplifier

Fig 4.1 Plots of op-or. 5".“ anip aJ a iunenun U1 we inversion

,Coefficient ICI and IC6 of transistors MI and M6 respectively, using minimum MOSFET channel length (L) in 1.2 ji Technology

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Fig 4.3 Output resistance of 2-stage op amp as a function of the inversion levels of transistors in the output stage

Fig 4.4 Offset voltage due to V T mismatch of the differential pair

Fig 4.5 Offset voltage due to V T mismatch and finite output resistance of the current mirror pair

Fig 4.6 Schematic diagram of a classical 2-stage CMOS operational amplifier Fig 5.1 Schematic diagram of a Simple Current Mirror (1:1)

Fig 5.2 Plot of current gain errors in Simple Current Mirror as a function of the

trop C; 0,11,* TII,X1LII.C:ess, 1 Cb• PP 1

Fig 5.3 Schematic diagram of Wilson Current Mirror

Fig 5.4 Schematic diagram of Improved Wilson Current Mirror

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LIST OF TALES

Table 2.1 ACM MODEL Parameters for N Channel MOSFET Table 2.2 ACM MODEL Parameters for P Channel MOSFET Table 2.3 Node Voltages at Operating Point (Cascode Stage) Table 3.1 First order MOSFET equations

Table3.2 Changes in Gain and Intrinsic Frequency of Common Source Amplifier due to changes in model and device parameters

Table 4.1 Common Performance Parameters of Operational Amplifiers (OP AMPs) Table 4.2 OP AMP Circuit Design Parameters for Numerical Example

Table 4.3 OP AMP Performance parameters obtained analytically using Advanced Compact MOSFET (ACM) Model and SPICE Simulation for 1.2

p

technology

Table 5.1 Simulation results for the Wilson Current Mirror

Table 6.1 Simulated performance of the Common Source Amplifier in 1.2

p

technology using SPICE BSIM parameters

Table 6.2 Simulated performance of the Common Source Amplifier with IC=400 in 0.35

p

technology using SPICE BSIM parameters

Table 6.3 Simulated performance of the Common Source Amplifier with IC=25

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r.

CONTENTS

CERTIFICATE

ACKNOWLEDGEMENT ABSTRACT

LIST OF SYMBOLS LIST OF FIGURES LIST OF TABLES

CHAPTER-1 INTRODUCTION AND SCOPE OF WORK 1

1.0 MOTIVATION 1

1.1 THE ACM (ADVANCED COMPACT MOSFET) MODEL 4

1.2 SCOPE OF WORK 11

1.3 ORGANIZATION OF THE THESIS 11

CHAPTER-2 ACM SMALL SIGNAL MODEL, WITH 13

SECOND ORDER EFFECTS

2.0 INTRODUCTION 13

2.1 THE MOSFET SMALL SIGNAL MODEL 13

2.2 ACM SMALL SIGNAL MODEL 15

2.3 TRANSCONDUCTANCS SENSITIVITIES 25

2.4 AN ILUSTRATIVE EXAMPLE OF MOSFET 31

ANALOG DESIGN

2.5 CONCLUSION 37

CHAPTER-3 MOSFET COMMON SOURCE AMPLIFIER DESIGN 38 TOWARDS MAXIMUM GAIN BANDWIDTH

3.0 INTRODUCTION 38

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CHAPTER-4 CMOS OPERATIONAL AMPLIFIER DESIGN USING ACM MODEL

4.0 INTRODUCTION 50

4.1 OPAMP DESIGN FORMULATION 52

4.2 OPAMP DESIGN PROCEDURE 67

4.3 A NUMERICAL EXAMPLE OF OPAMP DESIGN 69

4.4 CONCLUSION 73

CHAPTER-5 ANALYSIS

OF MATCHING ERRORS IN CURRENT 74 MIRRORS AT DIFFERENT INVERSION LEVELS

5.0 INTRODUCTION 74

5.1 ANALYSIS OF SIMPLE CURRENT MIRROR 76

5.2 ANALYSIS OF WILSON CURRENT MIRROR 81

5.3 RESULTS AND CONCLUSION 84

CHAPTER-6 OPTIMAL SCALING FOR LOW POWER 85

CONSUMPTION IN MOS ANALOG CIRCUITS

6.0 INTRODUCTION 85

6.1 POWER SCALING 87

6.2 LOW POWER SCALING PROCEDURE 90

6.3 NUMERICAL EXAMPLE 91

6.4 CONCLUSION 94

CHAPTER

-

7 CONCLUSIONS 96

7.1 MAIN RESULTS 96

7.2 SCOPE OF FUTURE WORK AND FURTHER

INVESTIGATIONS 97

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CHAPTER-1

• INTRODUCTION AND SCOPE OF WORK 1.0 MOTIVATION

In the past, the major concern of the VLSI designer was area, performance, cost and reliability; power considerations were of secondary importance. In recent years. however, this has begun to change and increasingly power is being given more weightage compared to area and speed.

Low power. yet high throughput and computationally intensive circuits are becoming a critical application domain. One driving factor being the trend in the growing class of personal computing devices (digital pens, audio and video based multimedia products). portable systems like pacemakers, as well as wireless communication and imaging systems which demand high speed computation, complex functionality and often real-time processing capabilities with low power consumption. Another critical driving factor is that excessive power consumption is becoming the limiting factor in integrating more transistors in a single chip or on a multi-chip module. Unless power consumption is drastically reduced. the resulting heat will limit the feasible packing and performance of VLSI circuits and systems. Circuit synthesized for low power are also less susceptible to run-time failures.

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Modern Application Specific Integrated Circuits (ASIC's) 'are increasingly becoming mixed signal types to realize system on chip (SOC) where digital and analog, circuits are integrated on the same chip. Low power reduction in digital is related to issues characteristic of digital design approach [I]. The present thesis is concerned with low power analog design where the related issues are

Issues Implications

• Voltage Scaling Compliance to maintain MOSFET in saturation

• Dimensional Scaling Short channel effects

• Subthreshold and Moderate region of operation.

Small range of operation

• Current mode operation New architectures

• Modeling standards and benchmarks Continuity in conductances and capaitances. Charge based, threshold based, potential based models.

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Moderate and weak inversions are increasingly important and unavoidable regions for device operation in integrated circuits using advanced CMOS technologies.

Scaling trends in deep submicron technologies limit the available range of voltage in strong inversion due to supply-voltage reduction and threshold voltage non-scalability. On the other hand, operation in moderate inversion is attractive in terms of increased transconductance efficiency and voltage gain.

In most of the work reported in literature [2,3,4,5,6], analog circuits have been designed using traditional, empirical MOSFET models wherein different sets of equations are used for devices operating in strong and weak inversion with discontinuity in moderate inversion, thus incurring severe errors in these important operating regions. With the scaling of device feature size and supply voltage, the level of inversion of MOS devices, also known as inversion coefficient (IC) and defined as the ratio of the drain saturation current to the intrinsic current which is proportional to the W/L ratio of MOS transistor, vary in a given circuit requiring single piece device model valid for all inversion levels.

In recent years, some attempts of MOS modeling have been made to have one- equation model for all the operating regions. [7][8][9][10]. EKV [11] based model uses extrapolation, surface potential based models such as MM1 1 [9]

requires heavy computational overhead and SPICE[8] has evolved to become empirically driven, complex and regional leading to continuity problems in transition regions requiring non-physical smoothing function .

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1.1 The ADVANCED COMPACT MOSFET (ACM) MODEL

MOSFET models included in circuit simulators can be classified into the following three categories:

• Analytical model

• Stable lookup models

• Empirical models

Most of the models in current use are analytical. MOSFET analytical models are based on either the regional approach or surface potential formulations, or semi-empirical equations. Models based on the regional approach use different

set of equations to describe the device behavior in different regions. In the regional approach, the weak and strong inversion regions are generally bridged by using a non-physical curve fitting[l 1]. Models based on surface potential formulation are inherently continuous; however, they demand the solution of an implicit equation for the surface potential. Semi-empirical models take the risk of becoMing neither scalable nor suited for statistical analysis. The ACM Model is a charge-based physical model. All the large-signal characteristics (currents and charges) and the small-signal parameters ((trans)conductances and (trans)capacitances are given by single-piece expressions with infinite order of continuity for all regions of operation. The ACM model preserves the structural source-drain symmetry of the transistor and uses a reduced number of physical parameters. It is also charge-conserving and has explicit equations for the MOSFET (trans)capacitances.

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The features of the ACM model can be summarized as follows:

• • single-piece expressions with infinite order of continuity for all regions of operation

• source-drain symmetry of the transistor

• charge-conserving equations

• phySically based . equations for the dependence of carrier mobility on tranversal field, carrier velocity saturation, and saturation voltage

• dependence of electrical parameters on geometry

• independence of technology

• easily measurable parameters

Some advantages of the ACM Model over BSIM are the use of simpler expressions to describe all regions of operation, the symmetry of the MOSFET is maintained, and requirement of a smaller number of device parameters.

Moreover, all the ACM parameters have a strong physical basis.

The Advanced Compact MOSFET (ACM) model is thus a current based model proposed in [10] ,with one-equation for all regions including weak, moderate and strong inversion. The first-order ACM model has been successfully applied in low power analog design [7][10][12][13]. In addition to its computer- implemented version [14] where most of the equations are charge based, it is also extremely useful for analog design by hand calculations.

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1.1.1 The ACM First Order Model

ACM is a physics based MOSFET Model described by a small set (approx.

11) of parameters [15]. The use of the substrate voltage as the reference voltage allows for a symmetric role of source and drain. Hence ACM is appropriate to simulate low-voltage circuits and those sensitive to charge variations.

In most analog applications, MOSFETs are biased in the saturation region of operation to achieve high transconductance and low output conductance.

The first order ACM model predicts a drain current (' D ) in saturation and at all levels of inversion that is given by the equation [10]

I D In

VPO — V

+ e t (1 + os )

where

V

=

V G

V

TO

(1.2)

PO

is the pinchaf voltage in equilibrium; V G ,V s are the gate and source voltages respectively with respect to bulk (substrate); V[)s is the voltage between drain and source; V 1.0 is the threshold voltage in equilibrium, 2 is the channel length modulation parameter; W and L are the width and length of the MOS transistor,

cl), is the thermal voltage , n is the subthreshold slope factor slightly dependent on V G , greater than one and usually less than two (derivative of gate voltage with respect to pinch-off voltage).

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The intrinsic current I„ and the inversion coefficient (IC) are defined by the equations

,2

1. ,u„nC (),

2 (1.3)

IC = Id = Id W

L

(1.4) where C is the gate oxide capacitance/ unit area, t' is the low field mobility and I is the normalized current also known as the specific current.

The Inversion Coefficient (IC) indicates the inversion level of the transistor.

weak inversion

I< /C5100 - moderate inversion and ic>loo - strong inversion

The expression for terminal voltages of the MOSFET in saturation in terms of the inversion coefficient is derived in [10] as

( )[-11+ IC 2 + In(V1 + /C — IA for nmos(pmos) (1.5)

VDsat — VP

= (—)[1n(V1 + IC -I)-5] for nmos(pmos) (1.6)

The three small signal parameters : gate transconductance (g ngb), drain conductance (g db ) and source transconductance (2 ) can be obtained by the differentiation of eq(1.1) as follows.

ID

:54 nigh = 6V (I D /70 VI /C I gb

(1.7)

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1 = 1 D nub (

sb

)

D 01 + K ' + I • (1.9)

1.1.2 The ACM Second Order Model

Although the first order model provides an analytic point of view for circuit design, it yields poor representation of MOSFETs with even moderate widths and lengths, since important second order effects are neglected.

A more complete and complicated ACM model considering second order effects is described in [14] using charge based equations. This model provides a representation of following second order effects.

Vp dependence on V o V s due to drain induced barrier lowering.

• Surface mobility reduction by gate induced vertical field

• Surface mobility reduction due to carrier velocity saturation

• Dependence of /1 upon operating point.

In the saturation region, the drain current I DS considering second order effects is given as

w

DS dd

L • (1.10)

where intrinsic current / 0„ pinch-off voltage V 1, and channel shortening factor AL + L

- dd , which model small geometry effects, are functions of bias. It AL + L

should be noted that if / os is replaced by 1 0 and (1 dd )- is replaced L

by (1 + 2.1/ D ) then eq(1.10) will reduce to the first order current eq(1.1). The term models the second order effects of surface-mobility modulation and

-os / L AL + L In I +e P -

-tv

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AL + L

dd is given as

L

(a) Channel Length Modulation

As modeled in [14) ,the channel shortening factor

where

AL +

L dd 2(LD) + L dd

L L

V — V DsAT Ldd = ALc ln[l + DS

Lc.UCR1T

UCRIT-v MAA.

/4) L c

AL, is the shrink in channel length, X. is the Junction depth, LD is the Lateral diffusion, is is the permitivity of S, UCRIT is the longitudinal critical field for mobility degradation, V MAX is the saturation velocity (m/sec) , pt o is the low field mobility (cm 2/V.$)

Also L e, = L — AL — L dd where .1_, 11 is the effective

(b) Drain Induced

Considering DIBL V1. = V1.'0 +

n

where VP0

n =1 +

channel length.

Barrier Lowering (D1BL)

effect the pinchoff voltage

+ V„

is obtained as

— PHI

\2

(1.15)

(1.16)

(1.17)

(1.18)

2 —

VG

V" )

(V

PHI

2-1

2 2

2V PHI +111

V.1.0 is the threshold voltage in equilibrium,y(GAMMA) is the body effect

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P

(1.20) VP-VS

1+e 119 '

49 1

1+ In

L eg UCRIT

43

dOs

=-

1+ 1-1 6 1+

VMAX dx UCRIT dx

=

11 0 Wen' CI) -

nC ox

\1+0y.\/Vp +PHI, L eq 2 VPVs I + (P,

L «^ UCRIT In 1 I)

(19

1+e , (1.21)

V P — Vs -1 1+e (Pt 11n

dependence of pinchoff voltage on V D and is set to zero the drain induced barrier loweririg effect is eliminated, then eq(I.15) reduces to the pinch off voltage of the first order model as is given by eq(1.2) •

(c) Mobility degradation effect

Mobility depends upon the vertical surface electric field, and decreases for large values of pinchoff or gate bias voltages. This is modeled by the equation

= IA 0

I-1

1 +07 .\IV + PHI

O(THETA) is mobility reduction coefficient due to transversal field.

(1.19)

(d) Effect of Velocity saturation

Velocity saturation of channel carriers lowers the device conductance and is modeled in ACM as

where Os is the surface potential

The drain current expression for MOSFET in saturation considering second order effects can be rewritten as

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1.2 SCOPE OF WORK

The work presented in the thesis evolves around the following topics:

Development of ACM small signal parameter model considering second order effects valid for all levels of inversion (strong, moderate and weak).

2. Design and performance of single transistor amplifier configuration for different inversion levels and determination of optimum transistor inversion level for maximum gain for a given unity gain frequency fr .

3. Development of design guidelines for a 2-stage CMOS operational amplifier to meet given specifications without any design iterations and valid for all levels of inversion.

4. Study of mismatch errors for the standard current mirror configurations at all inversion levels.

5. Development of scaling rule for MOSFET with reduction in power consumption and its application to an amplifier design.

1.3 ORGANIZATION OF THE THESIS

The work presented in the thesis is organized in 7 chapters contents of which are briefly given below.

• Chapter 1 introduces the rationale of investigating low-power CMOS analog design at different inversion levels. Motivation and need of development study of the analog blocks viz. MOS amplifier, operational amplifier and current mirror are justified.

• Chapter-2 describes the development of the small signal MOSFET model considering second order effects. The second order effects such as CLM, DIBL. and velocity saturation are represented as different components

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• In Chapter-3, the single stage amplifier design is optimized for maximum gain Bandwidth. The common source amplifier is found to give maximum gain at a given unity gain frequency J. when operated at an optimum -inversion level of 90.

• Chapter 4 gives the details of 2-stage CMOS operational amplifier design. Analytical expressions using the ACM (Advanced Compact MOSFET) model valid for all inversion levels are derived for all the parameters of the operational amplifier and design guidelines were developed for meeting given specifications of operational amplifier.

• In Chapter 5 development of practically useful formula, for estimating the nominal value of direct current transfer ratio a and the tolerance limits on it, arising from mismatches in operating conditions and dc parameters of the MOS transistors used in standard current mirrors, at different inversion levels, is presented

• The optimum scaling for reduction in power consumption is described in Chapter 6. The scaling laws are applied to single stage amplifier . using the ACM model.

• Finally, conclusions and future scope of work is summarized in Chapter-7

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CHAPTER-2

ACM SMALL SIGNAL MODEL WITH SECOND ORDER EFFECTS

2.0 INTRODUCTION

In many analog applications, the variation of voltages and currents in the circuit are small compared to the dc operating point, so small-signal analysis can be used to determine circuit behavior. When small-signal analysis is indeed valid, tractable analysis without computer aids is possible, and direct calculation of frequency-domain behavior can be performed. Analysis of the circuit then reduces to the much simpler task of analysis of an equivalent circuit.

2.1 THE MOSFET SMALL SIGNAL MODEL

Small signal analysis of MOS circuit involves approximation of the nonlinear MOSFET model illustrated in fig 2.1 with the linearized model illustrated in 1ig2.2. Analog CMOS design is further complicated by the dependence of small signal parameters of MOSFET on the operating bias conditions, inversion levels (strong, moderate, weak) and process parameters. Many articles on small signal MOSFET models have occurred in the literature [2,18] but they do not consider the second order effects. [19] does consider the second order effect but the model equations used are valid only for the strong inversion.

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D

S

Fig. 2.1 The Bulk referred MOSFET small signal model

(27)

Although the first order small signal model presented in [10] provides an analytic point of view for circuit design and is valid for all inversion levels, it yields poor representation of MOSFET's with even moderate widths and lengths, since important second order effects are neglected.

The present work explores the impact upon small signal performance of many second-order effects present in small geometry MOSFETs. Quantitative details of the small signal models are derived using the ACM model [10] in 1.2U CMOS technology and these models are related to their large signal counterparts.

2.2 MOSFET SMALL SIGNAL MODEL

Of interest here are the three small signal parameters: gmdb (drain/channel transconductance), g mo (gate transconductance), and g insb (source transconductance) with bulk (substrate) as reference.

2.2.1 Channel conductance gmdb

The channel conductance for a MOSFET in saturation can be obtained by differentiation of eq (1.1) as follows

I a D

a

g nidb =

(L eq) (IC)

Le D

q

av

D

eq op IC

av D

= g

dA, + g ddibl

where gobi and gddibl are defined as follows

Op

(2.1)

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1

I

g = (L - AL)

dA Leg

avD

AlI)

UCRIT * L Lc -

DSAT

L .UCRIT

1 D ddibl IC

av D

ID

(IC) )

/C 0 V L I D

o-I D 2 nOi vl + IC + I

Hence using equations (2.2) and (2.3) in equation (2.1) we have - D

mdb UCRIT * L

eg + VDS - VDSAT LC .UCRIT

01 D 2

n01 ./C + I

(2.4) The channel conductance g mdb results from channel length modulation and drain induced barrier lowering. Eq(2.4) is a generalization of the MOSFET output conductance for any bias condition. Channel length modulation effect component of g nidb , as modeled by g dm, depends only on the effective voltage drop across the shrunk part of the channel while the DIBL component, modeled by gd ( 1c ), depends on the current level or inversion coefficient IC(eq 1.3).

( IC ) op

(2.2)

(2.3)

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Table 2.1

ACM MODEL PARAMETERS FOR N CHANNEL MOSFET (1,21i)

L 1p.m W 800ptm

h`t 0

659 cm-/Vs LD 2e-9 m

PHI 0.8039 V VMAX 2.15e5 m/s

VTO 0.5957 V SIGMA 2.65e-12 m 2

XJ 3e-7 m TOX 2.99e-8 m

THETA • 0.0641 V - ' LAMBDA 1.21 /gm

GAMMA 1.2 V /2

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4

.

* •

el . r". C iletile r r

0

0.• --ddL ( component duet CLtyl)

4

0 --dd(dibl)(component due to DIBL)

f --gd (total channel conductance)

4

2 . F

ri

Q

2

IL

Lb

1

0.5

10 1 102

103

104

INVERSION COEFFICIENT (IC) —*

Fig. 2.2 Saturation Channel Conductance g dt, and its components at \f ps = 3 V and V sa = OV

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As shown in Fig 2.2 , using parameters in Table 2.1, of the two components the CLM component is the dominant component. The DIBL component attains

°ID

the maximum value of „ 0 and is independent of IC in weak inversion and increases in moderate inversion. For higher inversion levels then •DIBL component can be neglected compared to the CLM component.

2.2.2 Source transconductance g msb

The source tranconductance of a MOSFET in saturation can be obtained by differentiation of eq(1.1) as follows

D =

g d

(L 1

171Sb 171S0 Leg dl ey

Id 0 ( S

op p

I + d

— — (/C) op IC at . op

g b = g + g +g

1775 my) ins A M.ST ms1(..

where g „is° . g 'n75.1, and gmslc are defined as follows

gIns° - a (I a VD D

D 2

110 I + \I 1 + IC

g ms A L (Len- - Ldd)

eq s

- Al d UCRIT * L

ey + V DS -

DSAT Lc.UCRIT op

Id a

(2.5)

(2.6)

(2.7)

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(-)

s.) g

ID

msv av p op

( Vp — Vs \- -1 ni t I + e 1 0

a

aV D I + (p` In L e,UCRIT

ID

L eq UCRIT + C

g D

a

msdibl IC OV

a

(V )

IC av dV P

D 2

110 + IC + I

The first term g ms,0 results from the dependence of the drain current on the source voltage. The second term g„, s(A) is the result of dependence of channel length and CLM parameter on source voltage. g ms , is the result of the dependence of velocity saturation effect on the source voltage. For a long and wide transistor the pinch-off voltage is•a function only of gate voltage, but for short and narrow channel devices due to DIBL effect , V p becomes a function of V G' VS and V D measured with respect to bulk (substrate) resulting in g msdibl '

op

(2.8)

(2.9)

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--gmso (first order component) --gmsL (component due to CLM)

4 --gmsv (component clue to velocity saturation) 1:D --gmsdibl(component due to DIBL)

-f --curls (total source transconductance)

-+ 4

44' 4+44.4+

- 4 4 ..

—#

44 4

0.2 0:15

-O. 15

-0.2

-0 .1

100oo 101 10 -

INVERSION COEFFICIENT (IC)

1 04

Fig_. 2.3 Saturation Source Transconductance g msb and components at V DS 3 V

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I) a (fly.)

ft/ al . ti ') g

+ — — D a, 071 ,

Op n at .

g op D d

g = g (.

177g ) 171,0 p di op g

The source transconductance g nish and its components for the MOSFET is plotted in Fig 2.3. The first-order component g ins.° is a good estimate of

g las. for the weak and moderate inversion regions. The component due to

velocity saturation is important at higher inversion levels.

2.2.3 Gate transconductance g nio

The gate tranconthictance of a MOSFET in saturation can be obtained by differentiation of eq(1.1) as follows

g + g +

Ingo ingp nip? (2.10)

where g IVO • g i111.!11 • g igi. and gnIgn are defined as follows

g (I )

nigo at- D ID -2

11951 I + + IC 1

g = D

ingp p di"

g

op

op

(2.11)

- 11)07

I 1

1"po ,

0 2 j 0

po

(2.12)

(35)

1D p

/// l- I, al . II

• iu s

ID L eq UCRIT

t ,r/1:

op

(2.13)

1 D a (n)

`sign n at'

- IDr I

L eqUC'RIT V DS -

DSAT 1+ L

CUCRIT op

(2.14)

The first term g mgo is the first order representation of g no , while the terms g„,g,„•g,,,gi,.g„,g„ are due to the second order effects of, surface-mobility modulation, velocity saturation and subthreshold slope factor respectively. Using the parameter values listed in Table 2.1, g no and its components are plotted in Fig 2.4. The saturation voltage is =0,(V1+ IC —3) [10]. For inversion level 10 to 10 4 , the saturation voltage varies from 0.1 to 2.5V , hence 3V on the drain keeps the device in saturation throughout the whole plotted range.

Since g„,gi;-g„,g„ are negative, g „igb is degraded by the effects of surface mobility modulation and slope factor.

(36)

0,00

ill; NISI III IIauIIfl,iIull go

025

0.05

-cirficio (first order date trana::conductance) -drridu (mobility COmponent)

grridv (velocfty. saturation component) grridn (slope factor component)

(re:sultarit ':late trariSCOndUCtanCe)

M Et] Et LE 1111V3

10- U 3_ •04

INVERSION COEFFICIENT (IC)

Fig. 2.4 Saturation Transconductance

g mo

and components at \f ps 3V

(37)

2.3 TRANSCONDUCTANCE SENSITIVITIES

The variation of small signal transonductance g with respect to parameter P can be described by sensitivity S which is the percentage change in tranconductance P, with respect to parameter P. For small variations

Sp = P gor g oP

Both the small signal transconductances and the parameters P are positive.

A positive S ' implies that g is directly proportional to P. A largestarge of parameter ' P that cannot be precisely controlled implies that the circuit should be designed to be as insensitive as possible to variations in this parameter. A large S gP of parameter P that seldom changes is just a false warning.

A conductance 'g' has the highest sensitivity to the parameter which controls its dominant component. Since all three small signal transconductances are proportional to I s o , which is one of the controlling parameters of the first order terms in all three small signal conductance, the sensitivity S Is is unity.

2.3.1 Drain Conductance Sensitivities

1. Sensitivity to L

L

g • ) = —1

"V, ( "/(4)

d(A) g d(A) (2.15)

an increase/decrease in L results in a proportionate decrease/increase in g d(2) 2. Sensitivity to V [)

I •

Of,

(38)

I'I)

L c UCRIT + V Ds — os., 17 . 3. Sensitivity to A

A

Sc/(A) d(A)

4. Sensitivity to UCRIT

sUCRIT UCRIT

c/(A) g d(A) 0VUCRIT (g cl(A))

UCRIT

V '

UCRIT + D' ." 1

L ( • 5. Sensitivity to IC

IC 0 SIC

d(A) gd(A) %:IC' d(A))

IC.0,. I

=1 +

L c UCR1T +V Ds —I/ vs. ' ''. 2/1 + IC

(2.16)

(2.17)

(2.18)

(2.19) 6. Sensitivity to L c

Lc 0

S Lc L

gd (A) g d (A) °L• (gd(A))

L (I' Ds - osAT )UCRIT ( 2 Leg

_ 0.s. - DSAT ) L,

L eg UC'RIT + ---

L ( •UCRIT

(2.20)

(39)

gat

.;> ;`,'.>

gat

-1 41 41 =±.1 ;!:14 331-4114111111114=00111111

- 1

1 U it'

ce VD gd

.sy.)

1 03

1 02

-1.5

1 0 4

0 0 0 0 C. 0 0

vr..rcz, k

INVERSION COEFFICIENT (IC)

Fig. 2.5 Plots of Drain Conductance Sensitivities

(40)

For a device characterized by the model parameters in Table 2.1, drain conductance

17 ) Ic

sensitivities are plotted in fig2.6. Onlys 1,,; (11, . ‘3 ,

v- , . S;,1, and ' , 3 g db are - do ' •

vn ,-. I'

close to or greater than unity for all inversion levels with ' 5 , st, and o g(

d, being more predominant and increasing with increase in 'inversion level in the strong inversion region

2.3.2 Source Transconductance Sensitivities

1. Sensitivity to IC

S IC

gms .ems 'lc

IC ViC

2(1 + K')(1+ + IC) 2(L eg LICRIT + 0 1 V IC) 2. Sensitivity to L eg

.Leci Leg a

g ms g nu öLeq (g„,$)

.L eq UCRIT 1,,,„UCRIT +01VIC

(2.21)

(2.22)

3. Sensitivity to UCRIT

S UCRIT UCRIT

(g .) gms g„„ (.u•RIT In' s

(41)

4. Sensitivity to I,

a.) IC is maintained constant ie increasing Is with increasing Id gives a sensitivity of I

b.) Increasing I, with constant drain current results in reduced' IC

,o ab S^

g 5 Lmgb

is greater than unity at all inversion levels while and

s

mgb UCRIT

are appreciable only in the weak inversion region as seen in fig 2.6.

These results hold good for gate transconductances too.

(42)

sensiti%/ity to inversion coefficient Sensy to intrinsic current

- 4 sensitivity to channel lendth and LICRIT

z

44 4 4 4-4+444+4:

10 - 10

1.5

Lu

J.5

I—

F-

I

D.5

-1

11_1 LI

INVERSION COEFFICIENT (IC)

Fig 2.6: Plots of Source Transconductance Sensitivities

(43)

2.4. An illustrative example of MOSFET Analog design

Fig 2.7 shows the schematic of a' MOS cascode stage which generally Forms a part of a preamplifier . The numbers in paranthesis in Fig 2.7 are the channel widths and lengths. in microns. Fig 2.8 is the small signal equivalent circuit of the cascode stage. In the cascode stage the power supply is divided among the transistors, Ml. M2, M3 and M4. The cascode stage is very bias sensitive. Note V bi , in Fig2.8 is biased to adjust the dc level at the output node. Of interest here is the gain and 3dB frequency of this stage. All the devices are wide and short, with different channel widths and same lengths.

The set of model parameters characterizing the N channel enhancement devices M1 and M3 are listed in Table 2.1. The model parameters for the P channel enhancement devices M2 and M4 are listed in Table 2.2 . Using these parameters in Table 2.1 and 2.2, the cascode stage was simulated using the SPICE program.

The simulated node voltages at the operating point are listed in Table 2.3 . The devices' are biased such that VGS=1 to 2V and VDS=l to 4V.

2.4.1 Stage Gain and Pole Frequency.

The small signal equivalent circuit of the cascode stage is shown in fig . The loading conductances at nodes A and B , g and g /3 . are as follows

g g I gill, 2

g g‘//.4

(44)

VDD

M2 • M4

Output V13IAS

M3

C1

VIN

Vss M1

Fig 2.8 Schematic diagram of Cascode Stage

(45)

R

gdb3 Cgdl

go4 Cgs

gdh

Cgs 1 gm iVin

C d3

gdbl go2 bl

Vin

Fig 2.9. Small Signal Equivalent of Cascode Stage

(46)

Table 2.2

ACM MODEL PARAMETERS FOR P CHANNEL MOSFET

L l[tm W 165i,tm

0 273.55 cm 2/VS LD 9.09e-10 m

PHI 0.8039 V VMAX 1e6 m/s

VTO -0.78345 V SIGMA 2.65e-12 m 2

X.1 3e-7 m TOX 2.99e-8 m

THETA 0.0641 V - ' LAMBDA 4.95 /1.im

GAMMA 1.7 V ''2

Table 2.3

Node Voltages at Operating Point (Cascode Stage)

VDD 5.00V VSS 0.0V

Vbias 2.5V VIN 1.6V

V2 1.569V V5 3.6065V

(47)

Since the gate of M3 is at ac ground and its substrate is grounded, the effective source transconductance g ins.h3 and the channel conductance gd s.3 form the equivalent circuit of M3.

The ac gain of the cascode stage at low frequency can be obtained as follows.

A l • = — • -- • gm!

gc where gc• =gll g .((g dh3 /3) )

g db3 + g, „,sh3

The cascode stage can be modeled by a single 71- stage whose transconductance is g,,,, and is loaded by the output conductance g( .. Using the model parameters in Table 2.1 and 2.2 and the biases in Table 2.3, A, = 10.2 , g„„ =57.7mS,

g = 5.388mS and g l3 =3.39/77S g11 determines 80% of the output conductance. The simulated gain A, is identical to the calculated result. The high frequency gain G(s) can be obtained by replacing g A by g A + sC A and

g ll by g B +sCB . The result is

A (s) ,

as - + bs + c where

g =

C IC B

a = (g do + g • K )(g do + g ,71.s.3 )+gA g K

b = CAgK +CBgi ,

(g do + g K)(gdb3 +gms3)+gAgti

C = - g Agdb3 + g1gl.

(g + g K )(g do + g ms 3)+gA gK

and g g +

(48)

e

( . ..1 and C u are the loading capacitances at nodes A and B respectiyely.

C:I =

1 ,s;(11( 1

K) C ilbl C ghl C gs3 Cbs3

C 13 = C.gb4 4- g(/3I C 143 2 1.

K is the gain at node A and is obtained as gml gd3 + gin.v3

gc13( - )— (gdl + gd2 + gd3 — gm.v3) gd3 + go4

The loading capacitances are a function of the transistor widths and lengths and the source and drain layout. Neglecting the laoding capacitance C L assuming that sources and drains are rectangles of Wx2.5Um and using the junction capacitance parameters C m =0.894nF/cm 2 and C w=1.3552pF/cm. C A and C R are calculated as 1.54 and 0.39pF respectively. Both are approximately 60% .junction capacitance and 40% gate capacitance.

The pole frequencies fcl and fc2 are •

1 Cigk 13g1.

= 2n- a: A C /3 1± 1 4C .4 ( . 13(g .- i g do ± g Bg I.) (C' A g K +CB g L )'

In general C' 13 g L >C'A g A, and g„gi > g,g,„,3 . Taking the first order Taylor series expansion of the square root, the pole frequencies can be approximated by

L21 g

271C13

r g mg 3

./ 27rC

The pole frequencies are calculated to be 0.65GHz and 5.988GHz by using the exact expressions. The approximation gives a close estimate of the

K =

(49)

2.5 CONCLUSIONS

The MOSFET plays an important role in the design of analog circuits.

This chapter has presented first-order and second order MOSFET large signal model and has derived . corresponding small signal models and their sensitivities to model and technology parameters. from these large-signal models. The impact of prominent second order effects of small geometry MOSFETs upon small signal operation has been presented. It is seen that among the small-geometry effects, velocity saturation has the strongest impact on gate and source transconductances and the effect increases with increase in inversion level. The channel length modulation component determines 80% of channel conductance. The most sensitive model parameters affecting the transconductances were determined.

A cascode stage was analyzed as an example. In the circuit VGS is between 1 and 3V and among the small geometry effects, surface-mobility modulation and velocity saturation have the strongest impact on g gb and grnsb. It is seen in that inclusion of an appropriate expression for dominant second order effect in the output conductance correctly predicts the experimentally observed pole frequencies of the cascode stage.

(50)

CHAPTER-3

MOSFET COMMON SOURCE AMPLIFIER DESIGN TOWARDS MAXIMUM GAIN BANDWIDTH

3.0 INTRODUCTION

For analog design with scaled MOS transistors, current based approach is preferable which overcomes the problem of precise setting of gate voltage biasing reqUired in the conventional method. It is reported that in such a current biased MOS amplifier operated in the common source configuration , the maximum voltage gain for a given transition frequency (f. r. ), is obtained by operating the MOST in the moderate inversion region [13].The experimental observation indicates that for maximum gain the inversion level or inversion coefficient (IC) defined by the ratio of the drain saturation current 1 0 to specific current I s (IC —1 0/1,) should be around 80, whereas the first order theory predicted the inversion level to be IC = 8 [13].

Here we show that by considering the second order effect for the output conductance the optimal inversion level can be obtained analytically using single piece Advanced Compact Model (ACM) for a MOSFET valid for all levels of inversion [10]. The procedure enables sizing of W/L ratio of a MOS transistor used as common source amplifier for achieving maximum voltage gain for a given bandwidth.

(51)

3.1 MOS TRANSISTOR IN SATURATION AT ALL INVERSION LEVELS..

In high frequency MOS circuit designs short channels are very often used in combination with large gate voltages. Hence the degradation effects of''- the electrical fields in MOS transistor have to be considered. The drain current expression for a MOS transistor using ACM model including the second order effects is given in Chapter 1, Section 1.1.2.

The ACM model developed in [10] uses the normalized current I s known as specific current that contains the information of the device: geometry, technology and temperature and is given by.

2

=finC (3.1)

"

°t 2 L

In eq(3.1) W/L is the aspect ratio, m is the mobility, C o, is the oxide capacitance per unit area, 0 1 is the thermal voltage and n is the slope factor slightly greater than unity and almost bias independent [10]. Table 3.1 gives the first order MOSFET equations required for the amplifier design that are derived in [10] and reproduced here for convenience.

g mgh 1 2 g n g V A

, 7 = M

(3.3) ID .1101 I 41 + IC —(3.2) gds /D

1` = g mgh

Jr = PO ,

...(3 .4b) 27r( 1 . (3.4a)

— C WL) 2 OX

2(11+ IC —1) 27rL2

Table 3.1 : First order MOSFET equations

(52)

V US 2 --1

1 + e 11(P t

where - 1 d is the MOST drain current in saturation , jc is the inversion coefficient L is the length and W is the width of the MOS device.

The inversion coefficient of a saturated MOSFET is characterized by the normalized drain current IC—I D/I s or inversion level [10] and can be expressed in terms of bias voltages as

IC<l is weak inversion, I <IC<100 is moderate inversion and IC>100 is strong inversion.

In analog design. the transconductance is an important parameter. In Chapter 2 the transconductance g nio, considering second order effects is obtained as

/D 2 /DO' I I /D

mg 1)— sfrnA i I+ V I+ IC I + Orll% + 0 2 iv + + r

ni + 7 Le UCRIT + (p c\i/C (3.5)

po V po 2 q

For large values of IC the transconductance saturates to

Id 2 /d I I

cl

n01 VIC JP' +0 iv +0 +):

v V po

2

Considering the MOS transistor gate source capacitance[l0] for all inversion levels

C gs =

g na

(3.6)

WL (3.7)

(53)

The intrinsic frequency fr of the transistor can he defined as

//) 2 1 /)

nOt

1/7(7 \

II/Po

+ 0

+ + y Leg UCRIT + (pt NIC"

'g 171 = po

.1 r 2

ITC gs

2

- I

- + IC 4

/ n 11&

2-fij ° -NrIE + I 0

n0

V v

p0 + 0 I +0+Y Leg UCRIT +(p t

po

- C 2 3 ax WL

+ IC 4

(3.8) Hence for high frequencies, the higher the inversion level and the shorter the channel length L. the higher fr parameter can be achieved. In practical transistor designs extra capacitors exist, such as drain-bulk, source-bulk and overlap capacitors. They all decrease the ideal . To calculate these effects in a circuit design, the ratio of these capacitors to the gate source capacitance is calculated. The overlap capacitances are the capacitances between the gate and the source or drain. Hence they can be modeled as

Cgdov=C gsov C go W (3.9)

where Cg0 is a technology dependent parameter.

Hence the ratio C pos. / C gs is obtained as

(go lf

a gs0

3 ax L`

(54)

go

2\

114

+ /(.

This parameter is a strong function of the length. For designs using minimum lengths, this parameter is dependent on inversion level. For the'1.2[t technology parameters this ratio is about 0.09 forIC-1 and reduces for higher inversion levels.

The drain(source) bulk capacitance is dependent on the layout style. For the most simple straight structure it is obtained as

Cobb WL W. edge' dbj C -1-(W-1-2L edge) C dbjs%% (3.11) with L edge the drain (source) diffusion area length, C dbi the junction capacitance and C dbisw the side-wall junction capacitance. These parameters are all technology dependent, and as a result the designer can select only the transistor Width to make an impact on the bulk capacitance.

Cdb(bulk) WLedgeCdbj (W + 2L edge )C dbjsvi, db' 2 C •

• 3 + /C

4 (3.12)

As can be seen from the plot in Fig 3.1, a db(bulk) is nearly constant for different transistor widths and is a weak function of the inversion level.

adb(bulk) — Cgs.

1— 1

WL

(55)

0.012

0.0115

0.0095 1.0105 0.011

0.009 0.01

0 50 100 150 200

d- _L ' 4-

-F -F -F -F -F -F

250 300

a

IC

Fig 3.1 Plot of adb(bu/k) v/s Inversion Coefficient (IC) for different inversion levels.

(56)

gds "011+ V1+ IC eq LcUCRIT )1

gM I 1) 2 VDS I/D.S1-17.

-V AL 2 f

( UCRIT( +

Using the above it is easy to analyze real circuits. The —3dB point of a single transistor can be easily calculated as

(3.13)

-3d8 27r(C C gs„ C db) a g„ + adb

The capacitances due to interconnections can also be included in the above analysis, however since the effect of these parasitic capacitances can be drastically reduced by designing wide transistors, they are considered negligible compared to the other parasitics.

The transconductance to current ratio of a saturated transistor given by (3.2) is a universal relationship, which is independent of technology, dimensions and temperature. A , the attainable voltage gain of the common source amplifier can be written as in (3.3), where V A is the Early voltage which in a first order approximation, is proportional to the transistor channel length L. Finally, the intrinsic cutoff frequency of a MOSFET in saturation is approximated in [1]

by (3.4a) or, equivalently by (3.4b).

3.2 DESIGN EQUATION FOR MAXIMUM GAIN

Equations (3.2) , (3.3) and (3.4a) derived in [10] do not consider second order effects like CLM and DIBL. Considering the second order effects, the voltage gain expression of a common source amplifier can be written as

(3.14)

The equivalent channel length L eg required to achieve voltage gain A v is

, A v n Ot 1

(57)

Using (3.15) in (3.4h) we obtain

A1. 21117 All 1(.' —1 Vvs — V DSAT ) - _ (U( R1T +

..1 Nit VI /C + 1 LC

(3.16)

Taking derivative of voltage gain A w.r.t inversion Coefficient (IC) and A v )

equating to zero i.e. putting VA = 0 , from equ (3.16) we get a(IC)

(IC) = [—I — opt

2 — L c,UCRIT )] 2 —1

0/ 2 Ds (3.17)

Equ (3.17) gives an expression for the optimal inversion level for maximum gain for a given J. and is only dependent on the bias point for a given technology. Fig 3.2 shows the normalized theoretical gains, with and without the second order effect for intrinsic cutoff frequency of 2MHz, 20MHz and 200MHz. Simulation based normalized gain is plotted for intrinsic cutoff frequency of 26.9MHz and 103.4MHz using Cox'-2fF/m 2 , =500cm 2/V.s, VA-5V/

m. n=1.25, =25mV, UCRIT-2e6V/m,

The experimental observation indicate that for maximum gain the optimum inversion coefficient (IC) is approximately IC-85, the value obtained analytically is 1C-90 whereas the first order theory predicted the optimum inversion coefficient to be IC =8 [14

References

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