As indicated in the figure above, each of the characteristics

UNIT II

Graphical Representation of Transistor Characteristics

The figure given below shows the i_C-v_BE characteristics of a BJT

As in silicon diodes the voltage across the emitter-base junction decreases by about 2 mV for each rise of 1⁰ C in temperature, provided that the junction is operating at the constant current I as shown in the figure above.

T BE

V v S

C

I e

i 

The Common-Base Characteristics

One way to describe the operation of the BJT is to plot i_C versus v_CB for the various values of the current i_E. The characteristics is given below. (a) gives the circuit diagram and (b) gives the characteristics.

As indicated in the figure above, each of the characteristics

curves intersects the vertical axis at a current level equal to to

αI

, where I

is the constant emitter current at which the

particular curve is measured. The resulting value of α is total

or large-signal α, that is, α = i

/i

, where i

and i

denote total

collector and emitter currents, respectively. Here we recall that

α is called the common-base current gain.

Dependence of i_C on the Collector Voltage – The Early Effect

To see this dependence more clearly, consider the conceptual circuit shown below (a). The transistor is connected in the common-emitter configuration, that is, here the emitter serves as a common terminal between the input and output ports. The common-emitter characteristics is shown in (b).

At low values of v_CE, as the collector voltage goes below that of the base by more than 0.4 V, the collector-base junction becomes forward biased and the transistor leaves the active mode and enters the saturation mode. We observe that the characteristics curve, though still straight lines, have finite slopes. In fact, when extrapolated, the characteristics lines meet at a point on the negative v_CE axis at v_CE = - V_A. The voltage V_A, is positive number, is a parameter for the particular BJT, with typical values in the range of 50 V to 100 V. It is called the Early Voltage.

The linear dependence of i_C on v_CE can be accounted for by assuming that I_S remains constant and including the factor (1 + v_CE/V_A) in the equation for i_C as follows.

) 1

(

A V CE

v S

C

V

e v I

i

BE





The nonzero slope of the i_C – v_CE straight lines indicates that the output resistance looking into the collector is not infinite. Rather, it is finite and defined by

1 tan









 







 

CE C

o _BE

v

r i

We can show that for v_BE = V_BE

C A

o

I

r  V

V S

C

I e

I 

The output resistance r_o can be included in the circuit model of the transistor. This is illustrated in fig (a) and (b) below. Here we show the large-signal circuit

models of a common-emitter npn BJT operating in active mode. It may be

observed that D_B models the exponential dependance of i_B on v_BE and thus has a scale current I_SB = I_S/β . In (a) below voltage v_BE controls the collector current source, while in (b) the base current i_B is the control parameter for the current source βi_B. Here β is the common-emitter current gain.

The Common-Emitter Characteristics

An alternative way of expressing the transistor common-emitter characteristics is illustrated in figure below. Here the base current i_B rather than the base-

emitter voltage v_BE is used as a parameter.

An important parameter is the common-emitter current gain β. Consider the transistor operating in the active region at the point labelled Q as shown in Fig (b) above. The collector current at this point is I_CQ and base current as I_BQ and the collector voltage V_CEQ. The ratio of the collector current to base current is the large-signal or dc β.

BQ CQ dc

I

 I



B C

ac _CE

i i

 tan



 



Which is the β we have been using in our description of the transistor operation. It is commonly referred to on the manufacturer’s data sheets as h_fe . One can define another β based on incremental or small-signal quantities. So, keeping v_CE constant at point V_CEQ, changing i_B from I_BQ to (I_BQ + Δi_B) results in i_C increasing from I_CQ to (I_CQ + Δi_C). Thus we can write the incremental or ac β as β_ac .

The magnitude of β_ac and β_dc differ, typically by approximately 10% to 20%. Finally, it should be mentioned here that the small-signal β or β_ac is known by an alternate symbol h_fe. Because the small-signal β or h_fe is defined and measured at a constant v_CE, that is with a zero signal component between collector and emitter, it is known as the short-circuit common-emitter current gain.

The figure shows the typical dependence of β on I_C and on temperature in a modern integrated-circuit npn silicon transistor intended for operation around 1 mA. The value of β depends on the current at which the transistor is operating as shown by the above relationship. It also shows the temperature dependence of β.

An expanded view of the common-emitter characteristics in the saturation region

As can be seen from the figure the incremental β is lower in the saturation region than in the active region. A possible operating point in the saturation region is that labelled X. It is characterised by a base current I_B, a collector current Icsat and a collector -emitter voltage V_CEsat. Note that I_Csat < β_FI_B. Since the value of Icsat is established by the circuit designer, a saturation transistor is said to be operating at a forced β given by

B Csat forced

I

 I



F forced



 

The ratio of β_F to β_forced is known as the overdrive factor. The greater the overdrive factor, the deeper the transistor is driven into saturation and the lower the V_CEsat becomes.The collector to emitter resistance R_CEsat is given below.

Typically R_CEsat ranges between a few ohms to a few tens of ohms.

Csat C

B

B

I i I

i C

CE CEsat

i

R v _{ }



  _,

(a) An npn transistor operated in saturation mode with a constant base current I_B. (b) The i_C–v_CE characteristic curve corresponding to i_B = I_B. The curve can be approximated by a straight line of slope 1/R_CEsat.

MOSFET

Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.

Effect of v_DS on i_D in the saturation region. The MOSFET parameter V_A depends on the process technology and, for a given process, is proportional to the channel length L. Here λ is a process-technology parameter with the dimensions of V^-1 and for a given process, it is inversely proportional to L.

Temperature Effects

Both V_t and k’ are temperature sensitive. The magnitude of V_t decreases by about 2 mV for every 1^oC rise in temperature. This decrease in |V_t| gives rise to a corresponding increase in drain current as the temperature is increased. However, k’ decreases with the temperature and its effect is dominant one, the overall observed effect of a temperature increase is a decrease in drain current.

Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance r_o. The value of r_o is given by equations below

1

tan





 

 







 

t cons DS v

D o

GS

v r i

 

1 2 '

' 2

) 2 (

) 1

2 ( 1



 

 



 











t GS

n o

DS t

GS n

D

V L V

W r k

v V

L v k W i





where

Which can be written as

D A o

D

o

I

r V r  I  



1

Where I_D is the drain current without the channel-length modulation taken into account. That is

 

 

'

2 1 2

1

t GS

ox n

t GS

n

D

V V

L C W

V L V

k W

I     

Biasing in BJT Amplifier Circuits

The biasing problem is that of establishing a constant dc current in the collector of the BJT. This current has to be calculated, predictable, and insensitive to the variations in temperature and to a large variations in the value of β encountered among the transistors of the same type.

Attempting to bias the BJT by fixing the voltage V_BE by using a voltage divider across the power supply V_CC, as shown in figure below (a) is not viable approach. The very sharp exponential relationship i_C – v_BE means that any small and inevitable differences in V_BE from the desired value will result in large differences in I_C and V_CE. Secondly, biasing the BJT by establishing a constant current in the base, as shown in (b) below, where I_B ≡ (V_CC – 0.7)/R_B, is also not recommended approach. Here the typical large variations in the value of β among units of the same device type will result in corresponding large variations in I_C and hence V_CE.

Two obvious schemes for biasing the BJT: (a) by fixing V_BE; (b) by fixing I_B. Both result in wide variations in I_C and hence in V_CE and therefore are considered to be

“bad.” Neither scheme is recommended.

The Classical Discrete-Circuit Bias Arrangement

Figure (a) below shows the arrangement most commonly used for biasing a discrete-circuit transistor amplifier if only a single power supply is available. The technique consists of supplying the base of the transistor with a fraction of supply voltage V_CC through the voltage divider R₁, R₂. In addition, a resistor R_E is connected to the emitter. The figure in (b) below shows the same circuit with the voltage divider network replaced by its Thevenin equivalent.

Classical biasing for BJTs using a single power supply:

(a) circuit;

(b) circuit with the voltage divider supplying the base replaced with its Thevenin equivalent.

2 1

2 1

2 1

2

R R

R R R

R V R

V R

B

CC BB

 

 

The current I_Ecan be determined by writing a Kirchhoff’s loop equation for the base-emitter-ground, labelled L, and by substituting I_B= I_E /(β + 1):

) 1 /( 



 

B 

E

BE BB

E R R

V

I V

To make I_E insensitive to temperature and β variations, we design the circuit to satisfy the following two constraints:

 1







E

BE BB

R R

V V

Condition given above for V_BB ensures that small variations in V_BE (≈0.7 V) will be swamped by the much larger V_BB. There is a limit on how large V_BB can be: for a given value of the supply voltage V_CC, the higher the value of V_BB, the lower will be the sum of the voltage across R_C and the collector base junction (V_CB). On the other hand we want the voltage across R_C to be large in order to obtain high voltage gain and large signal swing (before transistor saturation). As a rule of the thumb, one designs for V_BB about 1/3 V_CC, V_CB (or V_CE) about 1/3 V_CC and I_CR_C about 1/3 V_CC.

Condition given by R_E makes I_E insensitive to variations in β and could be satisfied by selecting R_B small. This in turn is achieved by using low values of R₁ and R₂. Lower values of R₁ and R₂ will mean higher current drain from the power supply, and will result in lowering of the input resistance of the amplifier (if the input resistance is coupled to the base). Typically one selects R₁ and R₂ such that their current is in the range of I_E to 0.1I_E.

A Two-Power-Supply Version of the Classical Bias Arrangement

A somewhat simpler bias arrangement is possible if the two power supplies are available, as shown in figure below:

Biasing the BJT using two power supplies. Resistor R_B is needed only if the signal is to be capacitively coupled to the base. Otherwise, the base can be connected directly to ground, or to a grounded signal source, resulting in almost total β -independence of the bias current.

Writing the loop equation for the loop L gives:

) 1

( 



 

B



E

BE EE

E

R R

V I V

This equation is identical to equation of I_E given earlier except for V_EE replacing V_BB. Thus the two constraints of the equations given before apply here also. Note that if the transistor is to be used with the base grounded (i.e.) in the common-base configuration, then R_B can be eliminated altogether. On the other hand, if the input signal is to be coupled to the base, then R_B is needed.

Biasing Using a Collector-To-Base Feedback Resistor

Figures given below shows a simple but effective alternative biasing arrangement suitable for common-emitter amplifiers.

(a) A common-emitter transistor amplifier biased by a feedback resistor R_B.

(b) Analysis of the circuit in (a).

BE B

E C

E

BE B

B C

E CC

V I R

R I

V R

I R

I V

 











 1

Thus the emitter bias current is given by

) 1

( 



 

B



C

BE CC

E

R R

V

I V

It is interesting to note that this equation is identical to equation given earlier, which governs the operation of the traditional bias current, except that V_CC replaces V_BB and R_C replaces R_E. It follows that to obtain a value of I_E that is insensitive to variation of β, we select R_B / (β + 1) << R_C. Note that the value of R_B determines the allowable signal swing at the collector since

 1







CB

I R R

I

V

Biasing Using a Constant Current Source

The BJT can be biased using a constant current source I as indicated in the circuit of Figure (a) below. This circuit has the advantage that the emitter current is independent of the values of β and R_B. Thus R_B can be made large, enabling as increase in the input resistance at the base without adversely affecting bias stability. Further, current source biasing leads to significant design simplification.

A simple implementation of the constant current source is shown in Figure (b) below. The circuit utilizes a pair of matched transistors Q₁ and Q₂, with Q₁ connected as diode by shorting its collector to its base. If we assume that Q₁ and Q₂ have high β values, we can neglect their base currents. Thus the current through Q1 will be approximately equal to I_REF.

R

V V

I V I

R

V V

I V

BE EE

CC REF

BE EE

CC REF



 







  ( )

Since Q₁ and Q₂ have the same V_BE, their

collector currents will equal

resulting in I.

Neglecting the Early effect in Q₂, the collector current will remain constant at the value given by equation above as long as Q₂ remains in the active region.

This can be guaranteed by keeping the voltage in the collector, V, greater than that of the base (-V_EE + V_BE). The connection of Q₁ and Q₂ in the figure (b) above is known as a current mirror.

Biasing In MOS Amplifier Circuits

An essential step in design of a MOSFET amplifier circuits is the establishment of an appropriate dc operating point for the transistor. This is the step known as biasing or bias design. An appropriate dc operating point or bias point is characterized by a stable and predictable dc drain current I_D and by a dc drain-to-source voltage V_DS that ensures operation in saturation region for all expected input-signal levels.

Biasing By Fixing V_GS

The most straightforward approach to biasing a MOSFET is to fix its gate-to-source voltage V_GS to the value required to provide the desired I_D. This voltage value can be derived from the power supply voltage V_DD through the use of an appropriate voltage divider. Independent of how the voltage V_GS may be generated, this is not a good approach to biasing a MOSFET. To understand the reason for this statement, recall that

)

2 ( 1

t GS

ox n

D

V V

L C W

I   

And recall that the values of the threshold voltage V_t, the oxide-capacitance C_ox, and the transistor aspect ratio W/L vary widely among devices of supposedly the same size and type. Furthermore, both V_t and μ_n depend on temperature, with the result that if we fix the value of V_GS, the drain current I_D becomes very much temperature dependent. To emphasize the point that biasing by fixing V_GS is not good technique, we see in the figure given below that i_D – v_GS characteristic curves representing extreme values in a batch of MOSFETs of the same type. Observe that for the fixed value of V_GS, the resultant spread in the values of the drain current can be substantial.

The use of fixed bias (constant V_GS) can result in a large variability in the value of I_D. Devices 1 and 2

represent extremes among units of the same type.

Biasing by Fixing V_G and Connecting a Resistance in the Source

An excellent biasing technique for the discrete MOSFET circuits consists of fixing the dc voltage at the gate V_G, and connecting a resistance in the source lead, as shown in Figure (a)

Biasing using a fixed voltage at the gate, V_G, and a resistance in the source lead, R_S: (a) basic arrangement; (b) reduced variability in I_D;

(c) practical implementation using a single supply;

For the circuit in (a) above we can write

D S

GS

G V R I

V  

Now if V_G is much greater than V_GS, I_D will be mostly determined by the values of V_G and R_S. However, even if V_G is not much larger than V_GS, resistor R_S provides negative feedback, which acts to stabilize the value of the bias current I_D.

Equation above indicates that since V_G is constant, V_GS will have to decrease, for an increase in I_D for whatever reason. This in turn results in decrease in I_D, a change that is opposite to that initially assumed. Thus the of R_S works to keep I_D as constant as possible. This negative feedback action of R_S gives it the name degenerative resistance.

Figure (b) above provides a graphical illustration of the effectiveness of this biasing scheme. Here we show that i_D – v_GS characteristics for the two devices that represent the extremes of a batch of MOSFETs. Superimposed on the device characteristics is straight line that represents the connection imposed by the bias circuit as seen in the equation above. The intersection of this straight line with the i_D – v_GS characteristic curve provide the coordinate (I_D and V_GS) of the bias point. Observe that compared to the case of fixed V_GS, here the variability obtained in I_D is much smaller. Two possible practical discrete implementation of the bias scheme are shown in Figure (c) and (e).

(d) coupling of a signal source to the gate using a capacitor C_C1;

(e) practical implementation using two supplies.

The circuit in (c) utilizes one power-supply V_DD and derives V_G through voltage divider (R_G1, R_G2). Since I_G = 0, R_G1 and R_G2 can be selected to be very large (in MΩ range), allowing the MOSFET to present a large input resistance to a signal source that may be connected to the gate through a coupling capacitor as shown in (d) above. When two power supplies are available, the somewhat simpler bias arrangement of figure (e) can be utilized.

This circuit is an implementation of the Equation given above with V_G replaced by V_SS. Resistor R_G establishes a dc ground at the gate and presents a high input resistance to a signal source that may be connected to the gate through a coupling capacitor.

Biasing Using a Drain - to - Gate Feedback Resistor

A simple and effective discrete-circuit biasing arrangement utilizing a feedback resistor between the drain and gate is shown in the Figure below.

Biasing the MOSFET using a large drain-to-gate feedback resistance, R_G.

Here the large feedback resistance R_G (usually in MΩ range) forces the dc voltage at the gate to be equal to that at the drain (because I_G = 0). Thus we can write

D D DD

DS

GS V V R I

V   

Which can be written in the form

D D

GS

DD V R I

V  

Which is identical to the first equation, which describes the operation of the bias scheme above. Thus, here too, if I_D for some reason changes, say increases, then Equation above for V_DD indicates that V_GS must decrease. The decrease in V_GS in turn causes a decrease in I_D, a change that is opposite in direction to the one originally assumed. Thus the negative feedback or degeneration provided by R_G works to keep the value of I_D as constant as possible.

Biasing Using a Constant Current Source

The most effective scheme for biasing a MOSFET amplifier is that using a constant current source. Figure (a) given below shows such an arrangement applied to discrete MOSFET. Here, R_G (usually in MΩ range) establishes a dc ground at the gate and presents large resistance to an input signal source that can be capacitively coupled to the gate. Resistor R_D establishes an appropriate dc voltage at the drain to allow for the required output signal swing while ensuring that the transistor always remains in the saturation region.

A circuit for implementing the constant current source I is shown in Figure (b) below. The heart of the circuit is transistor Q₁, whose drain is shorted to its gate and thus is operating in the saturation region, such that

2 1

'

1

( )

2 1

t GS

n

D

V V

L k W

I  



 



 

Where we have neglected channel-length modulation (i.e. assumed λ = 0). The drain current of Q₁ is supplied by V_DD through resistor R. Since the gate currents are zero,

R

V V

I V

I









Where the current through R is considered to be the reference current of the current source and is denoted as I_REF. Given the parameter values of Q₁ and is a desired value for I_REF, Equations above can be used to determine the value of R.

Now consider transistor Q₂: It has the same V_GS as Q₁; thus we can assume that it is operating in saturation, its drain current, which is the desired current I of the current source, will be

2 2

'

2

( )

2 1

t GS

n

D

V V

L k W

I

I  



 



 



Where we have neglected channel-length modulation. Equations above enable us to relate the current I to the reference current I_REF as

 

 ^{W W L L} 

I

I 

Thus I is related to I_REF by the ratio of the aspect ratios Q₁ and Q₂. This circuit is known as the current mirror.