The First Computer

(1)

EE141 Introduction¹

Digital IC Design (EL-413)

Introduction

(2)

EE141 Introduction²

The First Computer

The Babbage

Difference Engine (1832)

25,000 parts

cost: £17,470

(3)

EE141 Introduction³

ENIAC - The first electronic computer (1946)

(4)

EE141 Introduction⁴

The Transistor Revolution

First transistor

Bell Labs, 1948

(5)

EE141 Introduction⁵

The First Integrated Circuits

Bipolar logic 1960’s

ECL 3-input Gate

Motorola 1966

(6)

EE141 Introduction⁶

Intel 4004 Microprocessor

1971

1000 transistors

1 MHz operation

(7)

EE141 Introduction⁷

Intel Pentium (IV) microprocessor

(8)

EE141 Introduction⁸

Moore’s Law

 In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months

 He made a prediction that semiconductor

technology will double its effectiveness every

18 months

(9)

EE141 Introduction⁹

Moore’s law in Microprocessors

400480088080 8085 8086

286 386

486 Pentium® procP6

0.001 0.01 0.1 1 10 100 1000

1970 1980 1990 2000 2010

Year

Transistors (MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel

(10)

EE141 Introduction¹⁰

Transistor Counts

1,000,000 100,000 10,000 1,000

10 100

1 1975 1980 1985 1990 1995 2000 2005 2010

8086

80286 i386

i486Pentium^®

Pentium^® Pro

K 1 Billion

Transistors

Source: Intel

Projected

Pentium^®II Pentium^®III

Courtesy, Intel

(11)

EE141 Introduction¹¹

Die Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)

(12)

EE141 Introduction¹²

Die Size Growth

40048008 8080

80858086 286386 486 Pentium ® proc P6

1 10 100

1970 1980 1990 2000 2010

Year

Die size (mm)

~7% growth per year

~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel

(13)

EE141 Introduction¹³

Frequency

P6

Pentium ® proc 486

286 386 8085 8086

8080 8008 0.1 4004

1 10 100 1000 10000

1970 1980 1990 2000 2010

Year

Frequency (Mhz)

Lead Microprocessors frequency doubles every 2 years

Doubles every 2 years

Courtesy, Intel

(14)

EE141 Introduction¹⁴

Power Dissipation

P6

Pentium ® proc 486

386 8086 286

80808085 40048008

0.1 1 10 100

1971 1974 1978 1985 1992 2000 Year

Power (Watts)

Lead Microprocessors power continues to increase

Courtesy, Intel

(15)

EE141 Introduction¹⁵

Power will be a major problem

5KW 18KW 1.5KW

500W

40048008808080858086286 386

486

Pentium® proc

0.1 1 10 100 1000 10000 100000

1971 1974 1978 1985 1992 2000 2004 2008 Year

Power (Watts)

Power delivery and dissipation will be prohibitive

Courtesy, Intel

(16)

EE141 Introduction¹⁶

Power density

4004 8008

8080

8085 8086

286 386

486

Pentium® proc P6

1 10 100 1000 10000

1970 1980 1990 2000 2010

Year

Power Density (W/cm2)

Hot Plate Nuclear Reactor Rocket Nozzle

Power density too high to keep junctions at low temp

Courtesy, Intel

(17)

EE141 Introduction

Device: The MOS Transistor

Gate oxide

n+

Source Drain

p substrate

Bulk contact

CROSS-SECTION of NMOS Transistor

p+ stopper Field-Oxide

(SiO

₂

) n+

Polysilicon

Gate

(18)

EE141 Introduction¹⁸ ₁₈

The Three Tenets

Input Gain Output Energy

(1)

Signal/

Noise

Input Output

(2)

Scalability, (3)

(19)

EE141 Introduction¹⁹

Why Scaling?

 Technology shrinks by 0.7/generations

 With every generation can integrate 2x more functions per chip; chip cost does not increase significantly

 Cost of a function decreases by 2x

 But …



How to design chips with more and more functions?



Design engineering population does not double every two years…

 Hence, a need for more efficient design methods



Exploit different levels of abstraction

(20)

EE141 Introduction

20

1.E-21 1.E-18 1.E-15 1.E-12 1.E-09 1.E-06 1.E-03 1.E+00

1940 1960 1980 2000 2020

Cubic Meter

Vacuum tube Transistor

NMOS

CMOS

Benefits of Scaling

1.E-11 1.E-09 1.E-07 1.E-05 1.E-03 1.E-01 1.E+01

1940 1960 1980 2000 2020 Delay (Sec) Vacuum tube

Transistor NMOS

CMOS

1.E-16 1.E-14 1.E-12 1.E-10 1.E-08 1.E-06 1.E-04 1.E-02 1.E+00

1940 1960 1980 2000 2020

Joules

NMOS

CMOS

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02

1940 1960 1980 2000 2020

Cost ($)

NMOS

CMOS

(21)

EE141 Introduction²¹

Design Abstraction Levels

n+

S

G

D +

DEVICE CIRCUIT GATE MODULE SYSTEM

(22)

EE141 Introduction²²

Cost of Integrated Circuits

 NRE (non-recurrent engineering) costs

 design time and effort, mask generation

 one-time cost factor

 Recurrent costs

 silicon processing, packaging, test

 proportional to volume

 proportional to chip area

fixed cost cost per IC = variable cost per IC + ---

volume

(23)

EE141 Introduction²³

Yield

% per wafer 100

chips of

number Total

per wafer chips

good of

No. 



Y

(24)

EE141 Introduction²⁴

Defects

area)

4