•The dc portion and

Chapter 2

BJT BIASING CIRCUIT

Introduction – Biasing

The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system. In fact, the amplifier increases the strength of a weak signal by transferring the energy from the applied DC source to the weak input ac signal The analysis or design of any electronic amplifier therefore has two components:

•The dc portion and

•The ac portion

During the design stage, the choice of parameters for the required dc levels will affect the ac response.

What is biasing circuit?

Biasing: Application of dc voltages to establish a fixed level of current and

voltage.

Purpose of the DC biasing circuit

• To turn the device “ON”

• To place it in operation in the region of its characteristic where the device operates most linearly .

•Proper biasing circuit which it operate in linear region and circuit have centered Q-point or midpoint biased

•Improper biasing cause Improper biasing cause

•„ Distortion in the output signal

•„ Produce limited or clipped at output signal

Important basic relationship

E C B

I = I + I

C B

I β = I

( 1)

E B C

I = β + I ≅ I

CB CE BE

V = V − V

Operating Point

•Active or Linear Region Operation Base – Emitter junction is forward biased Base – Collector junction is reverse biased Good operating point

•Saturation Region Operation

Base – Emitter junction is forward biased Base – Collector junction is forward biased

•Cutoff Region Operation

Base – Emitter junction is reverse biased

BJT Analysis

DC analysis

Calculate the DC Q-point

solving input and output loops

Graphical Method

AC analysis

Calculate gains of the amplifier

DC Biasing Circuits

•Fixed-bias circuit

•Emitter-stabilized bias circuit

•Collector-emitter loop

•Voltage divider bias circuit

•DC bias with voltage feedback

FIXED BIAS CIRCUIT

 This is common emitter (CE) configuration

 1 ^st step: Locate capacitors and replace them with an open circuit

 2 ^nd step: Locate 2 main loops which;

 BE loop (input loop)

 CE loop(output loop)

FIXED BIAS CIRCUIT

 1 ^st step: Locate capacitors and replace them with an open

circuit

FIXED BIAS CIRCUIT

 2 ^nd step: Locate 2 main loops.

1 2

1

2

BE Loop CE Loop

FIXED BIAS CIRCUIT

 BE Loop Analysis

1

■ ^{From KVL;}

I ^B

CC B B B 0

CC BE

B

B

E

V V

I

V

R V I R

−

∴ = −

+ + =

A

FIXED BIAS CIRCUIT

 CE Loop Analysis

■ ^{From KVL;}

■ As we known;

■ Substituting with ^{C B} I

I = β

2

I ^C

CC C C CE 0

CE CC C C

V I R V

V V I R

− + + =

∴ = −

B

A B

 

 



 −

=

B BE CC

DC

C

R

V I β V

Note that does not affect the value of Ic R

FIXED BIAS CIRCUIT

 DISADVANTAGE

 Unstable – because it is too dependent on β and produce width change of Q-point

 For improved bias stability , add emitter resistor to dc bias.

Collector–Emitter Loop

The collector–emitter section of the network appears in Fig. 4.5 with the indicated direction of current I_Cand the resulting polarity across R_C. The magnitude of the col- lector current is related directly to I_B through

I_C⫽␤^IB (4.5)

It is interesting to note that since the base current is controlled by the level of R_B andICis related to IB by a constant ␤, the magnitude of I_Cis not a function of the resistanceRC. Change R_C to any level and it will not affect the level of IB or ICas long as we remain in the active region of the device. However, as we shall see, the level of R_Cwill determine the magnitude of VCE, which is an important parameter.

Applying Kirchhoff’s voltage law in the clockwise direction around the indicated closed loop of Fig. 4.5 will result in the following:

VCE⫹ICRC⫺VCC⫽0

and V_CE⫽V_CC⫺I_CR_C (4.6)

which states in words that the voltage across the collector–emitter region of a tran- sistor in the fixed-bias configuration is the supply voltage less the drop across R_C.

As a brief review of single- and double-subscript notation recall that

V_CE⫽V_C⫺V_E (4.7)

where VCE is the voltage from collector to emitter and VC andVE are the voltages from collector and emitter to ground respectively. But in this case,since VE⫽0 V, we have

V_CE⫽V_C (4.8)

In addition, since

V_BE⫽V_B⫺V_E (4.9)

andVE⫽0 V, then

V_BE⫽V_B (4.10)

Keep in mind that voltage levels such as V_CEare determined by placing the red (positive) lead of the voltmeter at the collector terminal with the black (negative) lead at the emitter terminal as shown in Fig. 4.6. V_Cis the voltage from collector to ground and is measured as shown in the same figure. In this case the two readings are iden- tical, but in the networks to follow the two can be quite different. Clearly under- standing the difference between the two measurements can prove to be quite impor- tant in the troubleshooting of transistor networks.

Determine the following for the fixed-bias configuration of Fig. 4.7.

(a) IB_Q andIC_Q. (b) VCE_Q. (c) VB andVC. (d) VBC.

147 4.3 Fixed-Bias Circuit

EXAMPLE 4.1

Figure 4.5 Collector–emitter loop.

Figure 4.6 Measuring VCEand VC.

Solution

(a) Eq. (4.4): IBQ⫽ ᎏV_CC R

⫺

B

V_BE

ᎏ ⫽ ᎏ12 2 V

40

⫺ k

0

⍀

ᎏ ⫽.7 V 47.08␮^A Eq. (4.5): ICQ⫽␤^IBQ⫽(50)(47.08␮^A)⫽2.35 mA (b) Eq. (4.6): V_CEQ⫽V_CC⫺I_CR_C

⫽12 V⫺(2.35 mA)(2.2 k⍀)

⫽6.83 V (c) VB⫽VBE⫽0.7 V

V_C⫽V_CE⫽6.83 V

(d) Using double-subscript notation yields

VBC⫽VB⫺VC⫽0.7 V⫺6.83 V

⫽ⴚ6.13 V

with the negative sign revealing that the junction is reversed-biased, as it should be for linear amplification.

Transistor Saturation

The term saturationis applied to any system where levels have reached their maxi- mum values. A saturated sponge is one that cannot hold another drop of liquid. For a transistor operating in the saturation region, the current is a maximum value for the particular design.Change the design and the corresponding saturation level may rise or drop. Of course, the highest saturation level is defined by the maximum collector current as provided by the specification sheet.

Saturation conditions are normally avoided because the base–collector junction is no longer reverse-biased and the output amplified signal will be distorted. An oper- ating point in the saturation region is depicted in Fig. 4.8a. Note that it is in a region where the characteristic curves join and the collector-to-emitter voltage is at or be- low V_CEsat. In addition, the collector current is relatively high on the characteristics.

If we approximate the curves of Fig. 4.8a by those appearing in Fig. 4.8b, a quick, direct method for determining the saturation level becomes apparent. In Fig. 4.8b, the current is relatively high and the voltage V_CEis assumed to be zero volts. Applying Ohm’s law the resistance between collector and emitter terminals can be determined as follows:

R_CE⫽ ᎏV I

C C

ᎏ ⫽ ᎏE 0 IC

V

sat

ᎏ ⫽0⍀

148 Chapter 4 DC Biasing—BJTs

Figure 4.7 dc fixed-bias cir- cuit for Example 4.1.

EMITTER-STABILIZED BIAS CIRCUIT

 An emitter resistor, R _E is added to improve stability

 1 ^st step: Locate capacitors and replace them with an open

circuit

 2 ^nd step: Locate 2 main loops which;

 BE loop

 CE loop

Resistor, R E added

EMITTER-STABILIZED BIAS CIRCUIT

 1 ^st step: Locate capacitors and replace them with an open

circuit

EMITTER-STABILIZED BIAS CIRCUIT

 2 ^nd step: Locate 2 main loops.

1 2

2

BE Loop CE Loop

1

EMITTER-STABILIZED BIAS CIRCUIT

 BE Loop Analysis

■ ^{From kvl;}

Recall;

Substitute for I ^E

CC B B BE E E

0

V I R V I R

− + + + =

( 1) 0

( 1)

CC B B BE B E

CC BE

B

B E

V I R V I R

V V

I R R

β β

− + + + + =

∴ = −

+ +

B

E

I

I = ( β + 1 )

1

EMITTER-STABILIZED BIAS CIRCUIT

 CE Loop Analysis

■ ^{From KVL;}

■ ^Assume;

■ ^{Therefore; E C}

I

I ≈

CC C C CE E E 0

V I R V I R

− + + + =

2

)

( _{C E}

C CC

CE V I R R

V = − +

∴

Improved Bias Stability

The addition of the emitter resistor to the dc bias of the BJT provides improved stability, that is, the dc bias currents and voltages remain closer to where they were set by the circuit when outside conditions, such as temperature, and transistor beta, change.

( 1)

CC BE

c

B E

V V

I R R β

β

 − 

=   + +  

Without Re With Re

CC BE

c

B

V V

I _{= } ^ R ^{− } _ β

 

Note :it seems that beta in numerator canceled with beta in

denominator

For the emitter bias network of Fig. 4.22, determine:

(a) IB. (b) IC. (c) VCE. (d) VC. (e) VE. (f) VB. (g) VBC.

155 4.4 Emitter-Stabilized Bias Circuit

Solution

(a) Eq. (4.17): I_B⫽ ᎏ R_B

V

⫹

CC

(␤^⫺⫹ VB

1

E

)R_E ᎏ ⫽

⫽ ᎏ4 1

8 9 1

.3 k

V

ᎏ ⫽⍀ 40.1␮^A (b) I_C⫽␤^IB

⫽(50)(40.1␮^A)

⬵2.01 mA

(c) Eq. (4.19): VCE⫽VCC⫺IC(R_C⫹RE)

⫽20 V⫺(2.01 mA)(2 k⍀ ⫹1 k⍀)⫽20 V⫺6.03 V

⫽13.97 V (d) V_C⫽V_CC⫺I_CR_C

⫽20 V⫺(2.01 mA)(2 k⍀)⫽20 V⫺4.02 V

⫽15.98 V (e) VE⫽VC⫺VCE

⫽15.98 V⫺13.97 V

⫽2.01 V or V_E⫽I_ER_E⬵I_CR_E

⫽(2.01 mA)(1 k⍀)

⫽2.01 V (f) VB⫽VBE⫹VE

⫽0.7 V⫹2.01 V

⫽2.71 V (g) V_BC⫽V_B⫺V_C

⫽2.71 V⫺15.98 V

⫽ⴚ13.27 V (reverse-biased as required)

20 V⫺0.7 V ᎏᎏᎏ430 k⍀ ⫹(51)(1 k⍀)

EXAMPLE 4.4

Figure 4.22 Emitter-stabilized bias circuit for Example 4.4.

VOLTAGE DIVIDER BIAS CIRCUIT

 Provides good Q-point stability with a single polarity supply voltage

 This is the biasing circuit wherein, ICQ and VCEQ are almost independent of beta.

 The level of IBQ will change with beta so as to maintain the values of ICQ and VCEQ almost same, thus maintaining the stability of Q point.

 Two methods of analyzing a voltage divider bias circuit are:

 Exact method : can be applied to any voltage divider circuit

 Approximate method : direct method, saves time and energy,

 1 ^st step: Locate capacitors and replace them with an open circuit

 2 ^nd step: Simplified circuit using Thevenin Theorem

 3 ^rd step: Locate 2 main loops which;

 BE loop

 CE loop

VOLTAGE DIVIDER BIAS CIRCUIT

Simplified Circuit

Thevenin Theorem;

■ ^{2 nd} step: : Simplified circuit using Thevenin Theorem

2 1

2 1

2 1

//

R R

R R R

R R

+

= ×

=

CC

TH

V

R R

V R

2 1

2

= +

From Thevenin Theorem;

VOLTAGE DIVIDER BIAS CIRCUIT

 2 ^nd step: Locate 2 main loops.

1

2

BE Loop CE Loop

1

2

VOLTAGE DIVIDER BIAS CIRCUIT

 BE Loop Analysis

■ ^{From KVL;}

Recall;

Substitute for I ^E

TH B TH BE E E

0

V I R V I R

− + + + =

( 1) 0

( 1)

TH B TH BE B E

TH BE

B

RTH E

V I R V I R

V V

I R R

β β

− + + + + =

∴ = −

+ +

B

E

I

I = ( β + 1 )

1

VOLTAGE DIVIDER BIAS CIRCUIT

 CE Loop Analysis

■ ^{From KVL;}

■ ^Assume;

■ ^{Therefore; E C}

I

I ≈

CC C C CE E E

0

V I R V I R

− + + + =

) (

C CC

CE

V I R R

V = − +

∴

2

RTh: The voltage source is replaced by a short-circuit equivalent as shown in Fig. 4.28.

R_Th⫽R₁储R₂ (4.28)

ETh: The voltage source VCC is returned to the network and the open-circuit Thévenin voltage of Fig. 4.29 determined as follows:

Applying the voltage-divider rule:

ETh⫽VR2⫽ ᎏ R

R

1 2

⫹ V_C

R

C 2

ᎏ (4.29)

The Thévenin network is then redrawn as shown in Fig. 4.30, and I_BQcan be de- termined by first applying Kirchhoff’s voltage law in the clockwise direction for the loop indicated:

E_Th⫺I_BR_Th⫺V_BE⫺I_ER_E⫽0 SubstitutingI_E⫽(␤⫹1)I_Band solving for I_Byields

I_B⫽ ᎏ

R_Th E

⫹

Th

(

⫺

␤⫹ VB

1

E

)R_E

ᎏ (4.30)

Although Eq. (4.30) initially appears different from those developed earlier, note that the numerator is again a difference of two voltage levels and the denominator is the base resistance plus the emitter resistor reflected by (␤⫹1)—certainly very sim- ilar to Eq. (4.17).

OnceIB is known, the remaining quantities of the network can be found in the same manner as developed for the emitter-bias configuration. That is,

VCE⫽VCC⫺IC(R_C⫹RE) (4.31)

which is exactly the same as Eq. (4.19). The remaining equations for VE,VC, and VB

are also the same as obtained for the emitter-bias configuration.

Determine the dc bias voltage VCEand the current ICfor the voltage-divider config- uration of Fig. 4.31.

159 4.5 Voltage-Divider Bias

EXAMPLE 4.7

Figure 4.28 Determining R_Th. R₂

R_Th R₁

Figure 4.29 Determining E_Th. R₂ V_R E_Th VCC 2

+ – + –

R₁

Figure 4.30 Inserting the Thévenin equivalent circuit.

R_E E_Th

I_B

B

V_BE E R_Th

+ –

Figure 4.31 Beta-stabilized circuit for Example 4.7.

Solution

Eq. (4.28): R_Th⫽R₁储R₂

⫽ ᎏ3 (3

9 9

k k

⍀⍀

⫹ )(3

3 .9

.9 k

k

⍀

⍀

ᎏ ⫽) 3.55 k⍀

Eq. (4.29): ETh⫽ ᎏ R

R

1 2

⫹ V_C

R

C 2

ᎏ

⫽ ᎏ3 (

9 3.

k 9

⍀ k⍀

⫹ )(

3 2

. 2 9

V k⍀ ᎏ ⫽) 2V

Eq. (4.30): IB⫽ ᎏR_Th E

⫹

Th

(

⫺

␤⫹ V_B

1

E

)R_E ᎏ

⫽ ⫽

⫽6.05␮^A IC⫽␤^IB

⫽(140)(6.05␮^A)

⫽0.85 mA

Eq. (4.31): VCE⫽VCC⫺IC(RC⫹RE)

⫽22 V⫺(0.85 mA)(10 k⍀ ⫹1.5 k⍀)

⫽22 V⫺9.78 V

⫽12.22 V

Approximate Analysis

The input section of the voltage-divider configuration can be represented by the net- work of Fig. 4.32. The resistance Ri is the equivalent resistance between base and ground for the transistor with an emitter resistor RE. Recall from Section 4.4 [Eq.

(4.18)] that the reflected resistance between base and emitter is defined by Ri⫽ (␤⫹1)RE. If Ri is much larger than the resistance R2, the current IB will be much smaller than I2(current always seeks the path of least resistance) and I2will be ap- proximately equal to I1. If we accept the approximation that IBis essentially zero am- peres compared to I1orI2, then I1⫽I2andR1andR2can be considered series ele-

1.3 V

ᎏᎏᎏ3.55 k⍀ ⫹211.5 k⍀ 2 V⫺0.7 V

ᎏᎏᎏ3.55 k⍀ ⫹(141)(1.5 k⍀)

160 Chapter 4 DC Biasing—BJTs

Figure 4.32 Partial-bias circuit for calculating the approximate base voltage VB.

Approximate analysis:

2

2 2

( 1) 2 10

i R b

E E

R R I

R R

I

R R

β β

→

+ ⇒ >

 



If this condition applied then you can use approximation method .

This makes IB to be negligible. Thus I1 through R1 is almost same as the current I2 through R2.

Thus R1 and R2 can be considered as in series.

Voltage divider can be applied to find the voltage across

R2 ( VB)

Approximate Analysis

Then I _B << I ₂ and I ₁ ≅ I ₂ : When βR _E > 10R ₂ ,

From Kirchhoff’s voltage law:

2 1

CC B 2

R R

V V R

= +

E E E

R I = V

BE B

E V V

V = −

E E C

C CC

CE V I R I R

V = − −

) R (R

I V

V

I I

E C

C CC

CE C E

+

−

=

≅ This is a very stable bias

circuit. The currents and voltages are nearly

independent of any

variations in β.

VB⫽ ᎏ R

R

1 2

⫹ V_C

R

C 2

ᎏ (4.32)

SinceR_i⫽(␤⫹1)R_E⬵␤^RE the condition that will define whether the approxi- mate approach can be applied will be the following:

␤^REⱖ10R2 (4.33)

In other words, if ␤times the value of R_Eis at least 10 times the value of R₂, the ap- proximate approach can be applied with a high degree of accuracy.

OnceV_Bis determined, the level of V_Ecan be calculated from

VE⫽VB⫺VBE (4.34)

and the emitter current can be determined from IE⫽ ᎏV

R

E E

ᎏ (4.35)

and I_CQ⬵I_E (4.36)

The collector-to-emitter voltage is determined by VCE⫽VCC⫺ICRC⫺IERE

but since I_E⬵IC,

V_CEQ⫽V_CC⫺I_C(R_C⫹R_E) (4.37) Note in the sequence of calculations from Eq. (4.33) through Eq. (4.37) that ␤ does not appear and I_B was not calculated. The Q-point (as determined by I_CQ and VCEQ) is therefore independent of the value of ␤^.

Repeat the analysis of Fig. 4.31 using the approximate technique, and compare solu- tions for I_CQ andV_CEQ.

Solution Testing:

␤^REⱖ10R2

(140)(1.5 k⍀)ⱖ10(3.9 k⍀) 210 k⍀ ⱖ39 k⍀(satisfied) Eq. (4.32): V_B⫽ ᎏ

R R

1 2

⫹ VC

R

C

ᎏ2

⫽ ᎏ3 (

9 3.

k 9

⍀ k⍀

⫹ )(

3 2

. 2 9

V k⍀ ᎏ)

⫽2V

161 4.5 Voltage-Divider Bias

EXAMPLE 4.8

Note that the level ofVB is the same asEThdetermined in Example 4.7. Essen- tially, therefore, the primary difference between the exact and approximate techniques is the effect ofRThin the exact analysis that separates E_ThandVB.

Eq. (4.34): VE⫽VB⫺VBE

⫽2 V⫺0.7 V

⫽1.3 V ICQ⬵IE⫽ ᎏV

R

E E

ᎏ ⫽ ᎏ1 1

.5 .3

k V

ᎏ ⫽⍀ 0.867 mA compared to 0.85 mA with the exact analysis. Finally,

VCE_Q⫽VCC⫺IC(RC⫹RE)

⫽22 V⫺(0.867 mA)(10 kV⫹1.5 k⍀)

⫽22 V⫺9.97 V

⫽12.03 V versus 12.22 V obtained in Example 4.7.

The results for IC_QandVCE_Qare certainly close, and considering the actual vari- ation in parameter values one can certainly be considered as accurate as the other.

The larger the level of Ricompared to R2, the closer the approximate to the exact so- lution. Example 4.10 will compare solutions at a level well below the condition es- tablished by Eq. (4.33).

Repeat the exact analysis of Example 4.7 if ␤is reduced to 70, and compare solu- tions for I_CQ andVCEQ.

Solution

This example is not a comparison of exact versus approximate methods but a testing of how much the Q-point will move if the level of ␤is cut in half. RThandEThare the same:

RTh⫽3.55 k⍀, ETh⫽2 V

IB⫽ ᎏ

RTh

E

⫹

Th

(

⫺

␤⫹ V_B

1

E

)R_E ᎏ

⫽ ⫽

⫽11.81␮^A IC_Q⫽ ␤IB

⫽(70)(11.81␮^A)

⫽0.83 mA

VCE_Q⫽VCC⫺IC(RC⫹RE)

⫽22 V⫺(0.83 mA)(10 k⍀ ⫹1.5 k⍀)

⫽12.46 V

1.3 V

ᎏᎏᎏ3.55 k⍀ ⫹106.5 k⍀ 2 V⫺0.7 V

ᎏᎏᎏ3.55 k⍀ ⫹(71)(1.5 k⍀)

162 Chapter 4 DC Biasing—BJTs

EXAMPLE 4.9

DC Bias with Voltage Feedback

Another way to

improve the stability of a bias circuit is to add a feedback path from collector to base.

In this bias circuit

the Q-point is only

slightly dependent on

the transistor beta, β.

Base-Emitter Loop

) R (R

R

V I V

E C

B

BE B + CC β +

= −

From Kirchhoff’s voltage law:

CC C C B B BE E E

-V + I R +I R +V +I R ′ = 0 Where I _B << I _C :

I C I B

I C

I' C = + ≅

Knowing I _C = βI _B and I _E ≅ I _C , the loop equation becomes:

0 R

I V

R I R

I –

V _CC β _{B C} − _{B B} − _BE − β _{B E} =

Solving for I _B :

Collector-Emitter Loop

Applying Kirchoff’s voltage law:

I _E + V _CE + I’ _C R _C – V _CC = 0 Since I′ _C ≅ I _C and I _C = βI _B :

I _C (R _C + _RE ) + V _CE – V _CC =0 Solving for V _CE :

V _CE = V _CC – I _C (R _C + R _E )