DC Biasing - BJTs

DC Biasing - BJTs

CHAPTER 4

Introduction

• BJTs amplifier requires a knowledge of both the DC analysis (large signal) and AC analysis (small signal).

• For a DC analysis a transistor is controlled by a number of factors including the range of possible operating points.

• Once the desired DC current and voltage levels have been defined, a network must be constructed that will establish the desired operating point.

• BJT need to be operate in active region used as amplifier.

• The cutoff and saturation region used as a switches.

• For the BJTs to be biased in its linear or active operating region the following must be true:

a) BE junction  forward biased, 0.6 or 0.7V b) BC junction  reverse biased

Introduction

• DC bias analysis  assume all capacitors are open ckt.

• AC bias analysis :

1) Neglecting all of DC sources

2) Assume coupling capacitors are short ckt. The effect of these capacitors is to set a lower cut-off frequency for the ckt.

3) Inspect the ckt (replace BJTs with its small signal model).

4) Solve for voltage and current transfer function and i/o and o/p impedances.

• For transistor amplifiers the resulting DC current and voltage establish an operating point that define the region that can be employed for amplification process.

Introduction

• Important basic relationships for a transistor:

• V

=0.7V (1)

• I

= βI

+ (β+1)I

(2)

• I

≈ βI

(3)

•

• I

=I

+I

(4)

• or I

= βI

+I

• or I

= (β+1)I

(5)

BIAS STABILITY

In order to produce distortion-free output in amplifier circuits, the supply voltages and resistances in the circuit must be suitably chosen. These

voltages and resistances establish a set of d.c. voltage V_CEQ and current I_CQ to operate the transistor in the active region. These voltages and currents are called quiescent values which determine the operating point or Q-point for the transistor. The process of giving proper supply voltages and resistances for obtaining the desired Q-point is called biasing.

The circuits used for getting the desired and proper operating points are knows as biasing circuits.

V_CE

In Fig the values of V_CC and R_C are fixed and I_C and V_CE are dependent on R_B. Applying Kirchoff’s voltage law to the collector circuit in Fig. 1(a), we get

V_CC = V_CE+I_CR_C

• The straight line represented by AB in Fig. 1(b) is called, the d.c. load line.

i) The co-ordinate of the end point A are obtained by substituting VCE = 0 in the above equation.

I_C =V_CC / R_C

Therefore, the coordinates of A. are ( VCE = 0) and (I_C =V_CC / R_C)

ii) The coordinates of B are obtained by substituting I_C =0 in equation (1) then V_CE = V_CC

Therefore the coordinates of B are V_CE = V_CC and I_C = 0.

Thus, the load line AB can be drawn if the values of R_C and V_CC are known.

A shown in Fig. 1 (b), the optimum Q-point is located at the midpoint of the dc load line AB between the saturation and cutoff regions, i.e. Q is exactly midway between points A and B.

In order to get faithful amplification, the Q-point must be well within the active region of the transistor.

Even though the Q-point is fixed properly, it is very important to ensure that the

DC Load Line

(1)

In practice the, the Q-point tends to shift its position due to any or all of the following three main factors:

(1) Reverse saturation current, Ico which doubles for every 10°C increase in temperature (2) Base-emitter voltage, V_BE which decreases by 2.5 mV per °C

(3) Transistor current gain β, which increases with temperature.

Referring to Fig. 1(a), the base current I_B is kept constant since I_B is approximately equal to V_CC / R_B. If the transistor is replaced by another one of the same type,

It is not sure that the new transistor will have identical parameters as that of the first one.

Parameters such as β vary over a range. This results in the variation of collector current I_C for a given I_B. Hence, in the output characteristics, the spacing between the curves might increase or decrease which leads to the shifting of the Q-point to a location which might be completely unsatisfactory.

AC Load Line: After drawing the d.c. load line, the operating point Q is properly located at the center of the d.c. load line. This operating point is chosen under zero input signal condition of the circuit. Hence, the a.c. load line should also pass through the operating point Q. The effective a.c. load resistance, Rac_’ is the combination of R_C parallel to R_L, i.e.

Rac = R_C ll^r R_L. So the slope of the a.c. load line CQD will be – 1/ Rac

To draw an a.c. load line, two end points, viz, maximum V_CE and maximum I_C when the input signal is applied are required.

Thus,

V_CC = V_CEQ + I_CQR_a.c.’ which locates the point D (OD) on the V_CE axis.

Reasons for shifting of Q-point:

Operating Point

• For transistor amplifiers the resulting dc current and voltage establish an operating point on the characteristics that define the region that will be employed for amplification of the applied signal.

• Operating point  quiescent point or Q-point

• The biasing circuit can be designed to set the device operation at any of these points or others within the active region.

• The BJT device could be biased to operate outside the max limits, but the result of such operation would be shortening of the lifetime of the device or destruction of the device.

• The chosen Q-point often depends on the intended use of the circuit.

• Because the operating point, must lie on the load line, note that is stable if is stable

 ^V

^{, I}



V

I

15 18

12 9 6 3

I_C(mA)

V_CE(V) I_B=60 uA

10 20

I_B=50 uA

I_B=0 uA I_B=40 uA I_B=30 uA I_B=20 uA I_B=10 uA

40 A

C B

P_Cmax I_Cmax

Saturation

Various operating points within the limits of operation

of a transistor

Stability Factor

• The extent to which the collector current I_C is stabilized with varying I_CO , V_BE or / and β is measured by a stability factor.

• There are thus three types of stability factors.

• Stability Factor S

:

• Stability factor S^/ :The stability factor S^/ is defined as the rate of I_C with V_BE keeping I_CO and β constant.

• Stability factor S^// :The stability factor S^// is defined as the rate of change of I_C with respect to β keeping I_CO and V_BE constant.

Stability Factor (S)

• The extent to which the collector current I_C is stabilized with varying I_CO is measured by a stability factor S.

• It is defined as the rate of change of collector current I_C with respect to the collector base leakage current I_CO keeping both the current I_B and the current gain β constant.

The collector current for a CE amplifier is given by

Differentiating the above equation with respect to I_C, we get

Therefore, or,

From this equation, it is clear that this stability factor S should be as small (1)

(2)

Fixed-Bias Circuit

• For the dc analysis the network can be isolated from the indicated ac levels by replacing the capacitors with an open-circuit equivalent

because the reactance of a capacitor for dc is ∞Ω

• The dc supply V_cc can be separated into two supplies

Forward Bias of Base-Emitter

• Write KVL equation in the

clockwise direction of the loop : +V_CC – I_BR_B – V_BE =0

• Solving the equation for the current I_B results :

R_B

B

C

VBE E

V_CE +

+

- - IB

V_CC

Base-emitter loop +

-

B

BE CC

B

R

V - I  V

I_BQ

Collector-Emitter Loop

• The magnitude of the I_C is related directly to I_B through

I_C=βI_B I_CQ=βI_BQ

• Apply KVL in the clockwise direction around the indicated close loop results:

V_CE+I_CR_C-V_CC=0

V_CE = V_CC-I_CR_C => V_CEQ

• Recall that :

V_CE = V_C - V_E

• In this case, V_E = 0V, so V_CE=V_C

• V_BE=V_B-V_E Than V_E=0V, V_BE=V_E RC

VCE

+ -

VCC

I_C

Collector-emitter loop +

-

Differentiating w.r.t. I_CO

The collector current for a CE amplifier is given by

CO CO CO

B CO

C

dI dI dI

dI dI

dI  ( 1)

(1)

Since β is a large quantity hence this circuit provides very poor bias stability.

Stability Factor ‘S’

Example

Determine the following for the fixed bias configuration

a) I_BQ and I_CQ b) V_CEQ c) V_B and V_C d) V_BC Also find the value of the stability factor S.

β=50

Solution

  

  

reverse is

junction -

BC that indicates

sign ve

-

6.13V 83

. 6 7 . 0 )

V 6.83 V

V V

V 0.7 V

V )

83 . 6

2 . 2 2.35m -

12

R I - V

V )

34 . 2 08

. 47 50

I

08 . 240 47

7 . 0 12 )

C CEQ

CE

B BE

C C CC

CEQ CQ



































 



 

C B

BC

BQ

B

BE BQ CC

V V

V d c

V

k b

mA u

I k uA

R V I V

a



Example

Determine the following for the fixed bias configuration a) I

and I

b) V

c) V

d) V

e) V

f ) S

R_C=2.7kohm

B

C

V_BE E

V_CE +

+

- -

VCC=+16V

I_C

I_B

RB=470kohm

β=90

Solution

  

  

c

V

k b

mA u

I k uA

R V I V

a

BQ

B BE BQ CC

V 8.17 V

V d)V

V 0.7 V

V )

17 . 8

7 . 2 2.93m -

16

R I - V V

)

93 . 2 55

. 32 90 I

55 . 470 32

7 . 0 16 )

C CEQ

CE

B BE

C C CC CEQ

CQ























 



 



Transistor Saturation

• The term saturation is applied to any system where levels have reached their max values.

• For a transistor operating in the saturation region, the current is maximum value for a particular design.

• Saturation region are normally avoided because the B-C junction is no longer reverse-biased and the output amplified signal will be

distorted.

RC

VCE=0V +

-

VCC

ICsat

RB

+

-^VRC=VCC

The saturation current for the fixed bias configuration is:

I

R

V

• By referring to example 1 and the figure, determine the saturation level.

Solution

Example

limit.

the

within operates

I

that the concluded

be can

It . 34

. 2 I

in 1

example of

design

45 .

2 5 . 2

12

CQ

CQ mA

The

k mA R

I V

C Csat CC









• Find the saturation current for the fixed-bias configuration of figure example 2.

Solution

limit.

the

within operates

I

that the concluded

be can

It . 93

. 2 I

in 2

example of

design

92 . 7 5

. 2

16

CQ

CQ mA

The

k mA R

I V

C Csat CC









Example

Load-Line Analysis

• We investigate how the network parameters define the possible range of Q-points and how the actual Q-point is determined.

• Refer to figure below (output loop) one straight line can be draw at output characteristics. This line is called load line.

• This line connecting each separate Q-point.

• At any point along the load line, values of I_B, I_C and V_CE can be picked off the graph.

• The process to plot the load line is as follows:

R_C

V_CE +

-

V_CC I_C +

-

• Step 1:

Refer to circuit of Fig.1,

V

=V

– I

R

(1)

Choose I

=0 mA. Substitute into (1), we get V

=V

(2)  located at X axis

• Step 2:

Choose V

=0V and substitute into (1), we get I

=V

/R

(3)  located at Y-axis

• Step 3:

Joining two points defined by (2) + (3), we get straight line that can be drawn as in Fig. 2.

Load-Line Analysis

Applying KVL to output loop

I_C(mA)

V_CE(V)

Load line

V_CC/R_C

I_C=0 mA

V_CC

I_BQ Q-point

V_CE=0 V

Fig. 5.6

Load-Line Analysis

The point of

intersection of Load Line and the IB curve gives the Q- point

But which I_B will give the best Q-point values of I_C & V_CE called I_CQ and V_CEQ This is found from applying KVL to input loop:

BE CC

B

BE B CC

B B BE

CC

V V

R V I V

R I V

V

 

 





 0

2

I_C(mA)

V_CE(V) V_CC/R_C

V_CC

I_BQ2 Q-point

Fig. 5.7:Movement of Q-point with increasing levels of I_B

Q-point

Q-point I_BQ3

I_BQ1

Case 1:

• Level I_B changed by varying the value of R_B.

• Q-point moves up and down

Load-Line Analysis

I_C(mA)

V_CE(V) V_CC/R_C1

V_CC

I_BQ Q-point

Fig. 5.8 : Effect of increasing levels of R_C on the load line and Q-point

Q-point Q-point

V_CC/R_C2

V_CC/R_C3

R_C3 > R_C2 > R_C1

Case 2:

• V_CC fixed and R_C change the load line will shift as shown in Fig 5.8

• I_B fixed, the Q-point will move as shown in the same figure.

Load-Line Analysis

I_C(mA)

V_CE(V) V_CC1/R_C

V_CC1

I_BQ Q-point

Fig. 5.9: Effect of lower values of V_CC on the load line and Q-point

Q-point Q-point

V_CC2/R_C

V_CC3/R_C

V_CC2 V_CC3

V_CC1 > V_CC2 > V_CC3

Case 3:

• R_C fixed and V_CC varied, the load line shifts as shown in Fig. 5.9

Example

Given the load line of Fig. 5.10 and defined Q-point, determine the required values of V_CE, R_C and R_B for a fixed bias configuration.

15 18

12 9 6 3

I_C(mA)

V (V) I_B=60 uA I_B=50 uA

I_B=0 uA I_B=40 uA I_B=30 uA I_B=20 uA I_B=10 uA I_Cmax

Q-point _{IB=17 uA}

Solution

kohm 2311

17

7 . 0 40

I

V R V

R V - I V

kohm 67

. m 2

15 40 I

R V

0V.

V R at

I V

mA 0

I at V

40 V

V

B

BE CC

B

B

BE CC

B

C CC C

CE C

CC C

C CC

CE

: 2 Step

: 1 Step





 

 



















Example

Determine the value of Q-point for this figure. Also find the new value of Q-point if  changes to 150

.

RC=560ohm

B

C

V_BE E

V_CE +

+

- -

VCC=+12V

IC

I_B

RB=100kohm

100



  

  

 

  

^16.95m⁵⁶⁰

- 12

R I - V V

: 4 Step

mA 16.95

113 150

I I

same, is

value the

A 100k 113

0.7 - I 12

150, new

: 3 Step

mA 3 . 11 , V 67 . 5 int po Q

V 67 . 5

560 m

3 . 11 - 12

R I - V V

: 2 Step

mA 11.3

113 100

I I

A 100k 113

0.7 - I 12

100, : 1 Step

C C CC CE

B C

B

C C CC CE

B C

B























































The change of

 cause a big change of Q-point value.

This shows that fixed

biased

configuration is NOT stable

Solution

I_CQ & V_CEQ

Emitter Bias or Emitter-Stabilized Bias circuit

• The DC bias network below contains an emitter resistor to improve the stability level of fixed-bias configuration.

• The analysis consists of two steps:

- Examining the base-emitter loop (input loop)

- Use the result to investigate the collector-emitter loop (output loop)

Vi

Vo

R_C

C₁

C₂

V_CC

I_C

I_B

R_B

I_E

R_E B

E C

Base-Emitter Loop

R_B

B V_BE+ E

- I_B

V_CC

Base-emitter loop +

-

R_E

I_E

 

 

 

B

B B

R R

I I

1 V - I V

get, finally we

equation, the

Rearrange

0 R

1 -

V - R I - V

get, we

(1) into subtitute

, 1 I

known that

(1) 0 R

I - V

- R I - V

: KVL

BE B CC

E BE

B B CC

E

E E BE

B CC B



 





















- +

Collector-Emitter Loop or Output Loop

RC

C

VCE

+ -

V_CC IC

Collector-emitter loop +

-

IE

R_E

E BE

B B

B CC B

C C CC C

E CE

C

E C

CE

E E E

E C

C CC CE

C E

E E CE C

C CC

V V

V OR R

I - V V

R I - V V

OR

V V

V

V - V V

R I V

know can

also we Fig.5.13 the

From

) R (R

I - V V

get, we (1) equ rearrange

I I

Assuming

(1) 0 R

I - V - R I - V :

KVL





























Emitter resistor improves the stability level over the Fixed bias configuration by providing negative feed back and

+ -

B

C

E

+

V_BE -

From input loop From output loop

Stability Factor (S)

• The extent to which the collector current I_C is stabilized with varying I_CO is measured by a stability factor S.

• It is defined as the rate of change of collector current I_C with respect to the collector base leakage current I_CO keeping both the current I_B and the current gain β constant.

The collector current for a CE amplifier is given by

Differentiating the above equation with respect to I_C, we get

Therefore, or,

From this equation, it is clear that this stability factor S should be as small as possible to have better thermal stability.

(1)

(2)

0 R

I - V - R I -

V_{CC B B BE E E} 



Applying KVL to input side

0 R

I - V - ) R (R

I - V

I I

because

0 R

) I (I

- V - R I - V

E C BE

E B

B CC

C B

E C

B BE

B B CC













 I_E

Differentiating w.r.t. I_C :

) R (R

- R dI

dI

) R (R

R dI

- dI dI

dI

0 dI R

- dI ) R dI (R

- dI

E B

E C

B

E B

E C

C C

B

E C E C

B C

B

 

 





(3)

From equation(2) the stability factor is given as:

Putting the value of from equation (3) _dI^dI

C B

] R 1)

(R [ 1 1

1

] R ) R R

(R R R [

1

1

)] R (R

- R [ 1

1

E B

E E E

B E E

E B

E





 





 

 

 













S S S

If the ratio

E B

R

R ‹‹ i.e. v. v small & negligible



1 S =1

Example

For the emitter-bias network of Fig.1 determine:

a) I

b) I

c) V

d) V

e) V

f) V

g) V

R_C=2 kohm V_CC=+20V

I_C

I_B

R_B=430kohm

Fig. 5.14 ^{RE=1 kohm}

I_E

Beta=50

1

Solution

   

  

 

  

  

  

71 . 2 01 . 2 7 . 0 )

01 . 2 1

01 . 2

01 . 2 97 . 13 98 . 15 )

98 . 15 02 . 4 20

2 01 . 2 20 )

97 . 13

03 . 6 20 1

2 01 . 2 20

R R

I - V V

c)

mA 01 . 2 1

. 40 50 I

I b)

1 . 1 40

1 50 430

7 . 0 20 1

V - I V

a)

E C

C CC CE

B C

BE B CC

V V

V V f

V k

m R

I R I V

OR

V V

VC V

e

V

k m R

I V

V d

V

k k m

k A k

R R

E BE B

E C E E E

CE E

C C CC C

E B

































































 



 



 





 

Saturation Level

The saturation current for an emitter-bias configuration is:

R_C

V_CE=0V +

-

V_CC

I_Csat

Fig. 5.16

+ -

R_E

 

E C

CC Csat

E C

Csat CC

E Csat

C Csat

CC

R R

I V

R R

I V

R I

R I

V

 













0

0

Determine the saturation current for the network of example 7.

Solution:

 This value is about three times the level of I_CQ (2.01mA =50) for the example 7. Its indicate the parameter that been used in

example 7 can be use in analysis of emitter bias network.

mA 67

. k 6

3 20 k

1 k

2

20

R R

I V

E C

CC Csat



 



 

Example

The process to plot the load line as follows:

Step 1:

Refer to fig. 5.13, V_CE=V_CC – I_C(R_C+R_E) (1) Choose I_C=0 mA. Substitute into (1), we get

V_CE=V_CC (2)  located at X axis Step 2:

Choose V_CE=0V, substitute into (1) gives

axis Y

at located (3)

R R

I V

E C

CC

C



 

Load-Line Analysis

RC

C VCE

+

-

VCC

IC

Collector-emitter loop +

-

IE

RE

Step 3:

Joining two points defined by (2) + (3), we get straight line that can be drawn as Fig. 5.17:

I_C

V_CE(V) V_CC/(R_C+R_E)

V_CC

I_BQ Q-point

V_CEQ I_CQ

Load-Line Analysis

Voltage Divider Bias

• I

and V

from the table is changing dependently the changing of .

• The voltage-divider bias configuration is designed to have a less dependent or independent of the .

• If the circuit parameter are properly chosen, the resulting levels of I

and V

can be almost totally independent of .

 I

(  A) I

(mA) V

(V)

50 40.1 2.01 13.97

100 36.3 3.63 9.11

• Two methods for analyzing the voltage-divider bias configuration:

- Exact method

- Approximate method

Vi

Vo

RC

C1

C₂

VCC

R1

RE

R2

Voltage Divider Bias or Self Bias

Exact Analysis: Thevenin’s equivalent

• Step 1:

The input side of the network can be redrawn for DC analysis.

• Step 2:

Analysis of Thevenin’s equivalent network to the left of base terminal

R1

R_E R₂

Redrawn the input side of the network

Thevenin V_CC

B

• Step 2(a):

Replacing the voltage sources with short-circuit equivalent and gives the value of R

Exact Analysis

R₁

R2

RTH

Determining RTH

2

1

R

R

R



• Step 2(b):

Determining the E

by replacing back the voltage sources and open circuit Thevenin voltage. Then apply the voltage-divider rule.

R₁

R₂

V_CC V_R2

+

-

E_TH +

-

Determining E_TH

2 1

CC 2

2 R TH

R R

V V R

E   

Exact Analysis

• Step 3:

The Thevenin’s network is then redrawn and I

can be determined by KVL

0 R

I V

R I

E









 

T H

BE T H

B

R 1 R

V I E







 

Exact Analysis

R_TH

RE

Inserting the Thevenin equivalent cct.

ETH IE

I_B V_BE

+

-

C B

E

+

Now, I_E=I_C+I_B =βI_B + I_B I_E=(β+1)I_B

(1)

 ^{β 1}  ^{I in equation ( 1) gives}

I

Subtitute

 

Collector–Emitter Loop or Output Loop

• Applying KVL to the C-E or output loop gives

V_CE=V_CC – I_C(R_C+R_E) (2) V_CC –V_CE – I_CR_C- I_ER_E (1)

R_C

V_CE=0V +

-

V_CC

I_Csat

Fig. 5.16

+ -

R_E

+ - +

V_BE

-

I_E I_C

Taking I_E ≈ I_C and putting in equation (1)

V_CC –V_CE – I_CR_C - I_CR_E