 Minimize the noise figure

1

Design of rf System

(Transceiver) Building Blocks

Message Input

Message Output Antenna

The present unit shall deals with design of LNA & PA

In RF design frequency is high enough (>1GHz) to account for various parasitics (Aliens!)

How RF Design is different from anolog design (<1GHz)?

Cell phone radio

2

Parasitics (Aliens!)

Not sure! how to handle them?

Anolog designer (<1GHz)

Aliens(Parasitics)

Could manage them well?

rf designer (>1GHz)

Their TRUE nature is DISTRIBUTIVE, but they are quite often LUMPED for SIMPLICITY over personal WIRELESS BANDS (1-10GHz)

With new radio coming in 28/38/60/100 GHz bands in future…

Low power circuit designers have to upgrade their knowledge and learn how to deal with them!!

Design Objectives

 Minimize the noise figure

 Provide enough gain along with sufficient linearity.

 These blocks should present 50 to the outside world

If LNA is not excellent in noise then message is LOST.

+

Weak signal High noise

Crucial Blocks--LNA

LNA

S_in/N_in

G₁,NF₁ G₂,NF₂ ^GK,NF_K

S_out/N_out

G ...

G

1 NF

G

1 NF NF

NF

2 1

3 1

2

1

    



0 0

Withsufficient value of G1,overall NF is

decided by LNA

If NF of LNA is high, then signal might get LOST

Power Amplifier (PA)

Sufficiently high linearity &

efficiency Efficiency

enhancement

Linearity enhancement

Efficiency

Linearity

Long talk time High efficiency High data rate High linearity

Effort increase to linearity degrades efficiency vice versa.and

Impedance Level

Z_IN and Z_OUT are adjusted to 50vel through a technique called IMPEDANCE MATCHING

50 Z_IN  

LNA Or PA

Antenna

(50) Other

block (50)

50 Z_OUT  

Skills Required

Efforts have been made to develop these skills

Transceiver Architecture

Wireless

Standard CAD

Tools

Microwave Theory Communication

Theory

Abilities Needed

Expertise needed to be a good rf designer…

Design Flow

Specifications

Step-I

Which Device?

Step-II RF Circuit

No

Final

Yes If requirements are not met, then either circuit topology or device need to be changed with.

rf circuit is require

to satisfy the following requirements:

• Low power

• Noise

• Linearity

• Impedance

• Gain

Following steps are involved

Linearity

Gain Noise

Impedance Low Power

Efficiency

9

HBT

rf Circuits

BiCMOS

HEMT CMOS

Step-I:

CMOS

CMOS has been a dominant technology for personal wireless due to LOW POWER & LOW OCST

Step-II:

Choice of

circuit

CS has been shown to be a better choice due LOW

NOISE

Why CS?

t

i_g

G D

S



Noise currents i

, i

>>i



With CS configuration

 Significant portion of noise has been suppressed due to SOURCE

GROUNDING

Therefore, CS has

better noise performance

Why 50?

Simple answer: stages before and after LNA are at 50

e.g. filters, antenna etc.

50 

LNA Filter

50 

MOS circuits to realize 50 & their design

12

Option 1!

Zin

Common Gate

With proper value of g

, Z

can be made 50 but:

POOR NOISE

Z_IN1/g_m

g_mV_gs

R_L S

V_gs

+ -

Parasitics have been ignored for simplicity

Why POOR Noise?

t

i_g

G D

S



Noise currents i

, i

>>i



With CG configuration

 Less significant gate noise is

suppressed d due to GROUNDING

Therefore, CG has

POOR noise performance

14

Option 2!

Zin

VDD

R

Matching Network

V_gs

g_mV_gs R_L

G D

S Z_INR1

R1

With proper value of R₁, Z_in can be

made 50 but:

More

nosier

Matching Network

15

Improved Circuit!

L

RF

RF

L

V

s T

in

) L

Z

Re(  



Improved noise due to

 CS and lossless matching elements



50 could be easily realized



A low cost solution

How to achieve 50?

50

RFin 50Ω

Thevenins Equivalent See pages 376-378 of TH Lee Book

Matching Network

Equivalent Circuit

RF

L

L

R

V g

C

V

R

 50

 50 RF

Model Simplified

Z

v

i

Loop 1

R

& R

in rf model have been ignored for SIMPLICITY

Outside World

Outside World

Analysis

s gs m gs

g s

in in

in

) L

C ( g sC

) 1 L L

( i s

≡ v

Z    





 L 50

C ) g

Z

Re(

gs m in

gs s

g 0

in

( L L ) C

→ 1 0 ]

Z

Im[    

Real part can be adjusted to 50 by appropriate choice of Ls KVL in LOOP 1

gs in

gs

sC

v  i

in g s

gs m

gs

in

v [ 1 ( g sC ) sL ] sL i

v    

Real term without resistive element!

Im[Zin] =0 gives the frequency of operation of LNA

Next Issue!

Signal levels in anolog ICs are relatively higher than what they in rf ICs (~W or ~pW )

Therefore, noise in these designs e.g. LNAs. has to be ABSOLUTE MINIMUM.

Through, OPTIMIZATION noise can be further REDUCED

19

Noise Optimization

Y

DUT F

~

Source

Source admittance

   





2 opt s

s n

min G G B B

G F R

F   -  -

OPT S

OPT S

MIN i.e.B B &G G F

F  

Y_OPT

DUT

~

Source

Source admittance

With Y_OPT noise achieved is the lowest i.e. F_MIN

If this theory is applied to MOSFET, then Y_OPT is equal to:

See TH Lee for detail

 

  _



 



 







T 2

T

MIN

ω

2.3 ω 1

c - 1 ω γδ

ω 5 1 2

F ~





gs

OPT

1 - c

5γ αωC δ

G  B

 0

F_MIN has been achieved but power does not flow well because

G

 1/50)

Also, a larger width MOSFET is required to achieve G_OPT and associated power losses are HIGH.

Optimized result

Summary!

DUT

Input Output

But to achieve such noise performance, requires LARGE width W transistor, therefore, POWER losses are HIGH

With Y_OPT F=F_MIN

With W_OPT,P F=F_MIN,P

With judicious choice of width, noise can be made LOW as well as reduce the power losses .

How to determine W_OPT,P?

Optimum Width

!

50 C

L W

1 2

Q 3

OX

sp     



With optimum width W_OPT,P input quality factor Q_sp turns out to be 4.5 (Refer to page 382 of Lee book)

50 fLC

6 W 1

OX P

,

OPT  



RFin 50Ω Lg

Cgs

Ls

Input side 50

1



 

gs

sp C

Q



OX OX

OX T

C _



P OPT, sp 4.5 ; W W

Q  

W _OPT,P

) 6 (

1

,

k m GHz

R f LC

W

S OX P

OPT

    



k500 for typical state-of-art CMOS process under 50 system

,

500( )

opt P

W   f  m GHz 

Design Rule

 

 



 



T P

MIN,

ω

ω α

2.4 γ 1

F

With W=W_OPT,P noise obtained as:

F_MIN,P is the noise factor when there is a reduced power losses and F_MIN,P>F_MIN (See page 383 of TH Lee Book)

 

 



 



T P

MIN,

ω

5.64 ω 1

F

Question?

No……Why?

With G_OPT

Noise match

With G=1/50

Power match

Are noise and power matches simultaneously possible to achieve in LNA?

As their impedance levels are DIFFERENT!

G

 1/50

F _MIN,P Vs F _MIN

_T/ F_MIN F_MIN,P

20 0.5 1.1

15 0.6 1.4

10 0.9 1.9

5 1.6 3.3

F_MIN and F_MIN,P differ in the range of 0.5-1.0.

 

 



 



T P

MIN,

ω

5.64 ω 1

F

WWith_OPT,P

 

 



 



T

MIN

ω

2.3 ω 1

F

WithG_OPT

However, W_OPT,P is very attractive solution as it balances out critical parameters of interest very well.

LNA Design

Step-I

Determine the W_OPT,P and bias the device appropriately

Step-II

Select Ls for desired input match with given T at given bias

Step-III

 Finally calculate F_MIN,P

 Then add Lg to operate the circuit at desired frequency fo

Following steps are involved:

Design Exercise!

CGD

CGS gmV1

G

V1

LS

D

ZIN

 

f Z 2

Re

GS GD

S T

IN  



Step-I: Determine W_OPT,P W_OPT,P =208.33m

Step-II: Determine Ls to make Re (Z_IN) =50

F_MIN,P, _1.33

Step-III: Determine F_MIN,P & L_G

T P

MIN,

1 5.64 ω ω F  

GS S

G

0

1 2π 1 (L L )C

f  

L_S, _0.30nH

L_G, =???

Design LNA for Bluetooth. (2.4GHz) Take the MOSFET model as shown

MMIC

RFIC Inductor

Packaged IC Antenna

T ^{WO DAYS} T ^RAINING

MMIC Amplifier with Integrated Antenna Using IHP, PDK

ORGANIZED BY

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Venue: Computer Lab (2.11.2019 & 3.11.2019 ) Registration:

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Last Date:

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