Selected Topics in
Electronic Circuits and Systems (EL-821)
Prof. M. Shah Alam
Department of Electronics Engineering AMU Aligarh
E-mail: msalam.el@amu.ac.in
Starting: 17th Jan., 2017
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.. About your teacher
1988: Bachelor of Engineering (Electronics & Communication Engineering 1991: Master of Engineering (Electronics
& Communication Engineering
2002: Doctorate degree (Ph. D) (Electronics Engineering)
2010: Post doctorate (Nano-electronics)
http://www.amu.ac.in/dshowfacultydata2.jsp?did
=32&eid=3208
Visit website for more details:
Evaluation!
Course work:
Lecture/Seminar;
Quiz , Home work etc.
Final Semester Exam, 60%
Mid Semester Exam, 25%
Course Work, 15%
Books
B. Razavi, “RF Microelectronics”, 2nd edition, Prentice Hall, 2012.
T. Ytterdal, Y. Chang and T.A. Fjeldly, "Device Modeling for Analog and RF CMOS Circuit Design", Wiley, 2004
Ulrich L. Rohde and Mathias Rudolph "RF/Microwave Circuit Design for Wireless Applications“ Wiley, 2013
Kai Chang, Inder Bahal and Vijay Nair, RF and Microwave Circuit and Component Design for Wireless System, Wiley, 2002.
Y. P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw- Hill Inc, 1988.
T.H. Lee, "The Design of CMOS Radio Frequency Integrated Circuits", Cambridge University Press, 2004
References
M. S. Alam, Analytical Modeling and Design of CMOS LNA with ESD Protection, IETE Technical Review, Volume 32, Issue 3, 2015; pages 227- 235.
M. S. Alam, and G.A. Armstrong, Extrinsic Resistance Parameter Extraction and RF Modeling of CMOS, Solid State Electronics, Elsevier Publication, Volume 48, Issue 5, 2004, pp. 669-674.
Advanced
Semiconductor Devices
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Course Flow!
MOSFET -device physics
Part-I Part-II
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Course Flow!
How to
Develop device Model?
Part-III
Several solid-state DEVICES are being used to develop cell phone circuits……….which among them is the better choice?
Anolog/rf and digital circuits are required to build rf systems. The performance of these system depend on the device technology used.
How to make choice?
MOSFET
e.g. Cell phone system (transceiver)
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Low Noise-- Not add too much noise
Mature Technology -- Lower cost
Single Supply--- Make circuits less bulkier
High Efficiency -- Make circuits less bulkier
Low Power-- Ensure portability of system
Desirable Features
Ref: Chapter 3 of Kai Chang Book; pages: 37-82
Key Features!
BulkierLess
Lower Cost PowerLow
Cost is an important deciding FACTOR!
Options Available!
HBT
RF/Anolog Circuits
BiCMOS
HEMT CMOS
Which is better choice ?
These are the some of the potential technologies, which can
be tried!
CMOS
Performances can be further improved by reducing the size Mainstream IC Technology
High Integration Simple Processing Steps
Low Power Consumption Higher Speed
High Reliability
Low Noise Low Cost
Bi-CMOS
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CMOS
Bipolar
BiCMOS
Power Speed
Optimal cost for high performance
Higher speed Moderately good
integration level Bi-CMOS
utilizes best of bipolar and best of CMOS….
……Both at circuit and system levels
HBT: Hetero junction Bipolar Transistor
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Reasonable Cost
Noise is relatively High
Much better noise in SiGe has been achieved
Good Linearity Higher speed # Single Supply
# Primarily due to improved carrier velocity
Same material
(n-typeSi ) Si
(p-type) Si (n-type) E
B
C
AlGaAs
(n-type) GaAs
(p-type) GaAs (n-type) E
B
C
Different material
Make use of different materials and deliver improved performance
HEMT: High Electron Mobility Transistor
Make use of compound materials such as InP, GaAs etc.
Great diversity in the nature and performance of these devices due to selection of materials and doping
Operating range 10-100 GHz
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Higher linearity
Ultra low noise
Ex:
PCSSi 1-2 GHz
WLANSi 5 GHz
Micro LinkGaAs 28 GHz
Si is very muchused for1-5 GHz
Si preludes its use above 5 GHz , whereas GaAs may go upto 100GHz Ref: More details in Kai Chang Book; pages: 70-72
Question?
Each device technology has merits and demerits
Which device to select and why?
Criteria
Speed
Cost &
Maturity
Power Consumption
How to decide ?
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..At Glance
Parameter Better Moderate Poor
Integration CMOS BiCMOS, SiGe GaAs, HEMT
Cost CMOS BiCMOS, GaAs HEMT
Technology
maturity CMOS GaAs SiGe, HEMT
Speed HEMT CMOS, GaAs,
SiGe ---
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… At Glance
Parameter Better Moderate Poor
Power
consumption CMOS BiCMOS, SiGe GaAs
Noise Figure HEMT CMOS,
BiCMOS GaAs
CMOS has clear cut advantages over other device
technologies
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CMOS
Choice of Device
CMOS is most widely used technology
for rf/anolog due to Low Cost and Low Power HBT
RF/Anolog
BiCMOS
HEMT
CMOS
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MOSFET
Output impedance --Gain Threshold voltage Why these effects are important ?
As these affects could alter:
Leakage current etc…
Length of the order of depletion width !
As the channel length L is reduced to increase both
the operational speed and the number of
components per chip, then so-called short-channel
effects arise
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Channel Length Modulation (CLM)
Drain induced barrier lowering (DIBL)
Hot carrier effect
Substrate Current Induced Body Effect (SCBE)
Body Effect
Various Types
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CLM
Pinch-off
Effective length of MOSFET varies with drain voltage VD
Potential along the channel varies gradually i.e. GCA is assumed
y V
x
V
x
y
/ /
However, modern MOSFETs have extremely short channel
lengths, and this requirement is quite often not met.
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CLM
V-I characteristics of short channel MOSFET increases with increase in V DS due to CLM
The drain-channel interface depletion layer width X D increases with increasing drain-source voltage and modulates the channel length
is the channel length modulation parameter ( 1/L)
) 1
( )
(
GS T SAT DSox
D
WC V V v V
I
CLM need to carefully accounted as it affects both
current and output resistance of the MOSFET.
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DIBL
MOSFET with S and D depletion regions Pronounced as “ dibble"
In short channel
MOSFET depletion charge
under gate
not only
induced by
G but also
S & D
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DIBL
The device with long channel lengths, the gate is completely responsible for depleting the semiconductor (Q
B).
However, for short channel device, part of the depletion is accomplished by drain and source bias
Since less gate voltage is required to deplete Q
B,V
Tis lowered as L is decreased.
Similarly, as V
Dis increased, more Q
Bis
depleted by the drain bias, and hence V
Tis
further lowered.
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DIBL
However, if the channel length becomes too
short, the depletion region from drain can
reach the source and facilitates direct carrier
injection. This is known as “ PUNCH THROUGH ”
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The drain current is then dominated by the space-charge limited current which varies as V
D2. This current flows in parallel to the inversion layer current, which increases almost linearly with gate voltage but remains small compared to the space- charge limited current.
Consequently, the drain current of such devices fails to saturate even at large values of drain voltage V
DDIBL
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1
OX B F
FB
T C
V Q
V 2 Long Channel
1
OX B F
FB
T C
V Q
V 2
Short Channel
OX dep p
MS
TH
C
V 2 Q
OX dep p
MS
TH
C
V Q
2
a i
T
p V ln N n
MS=Work function difference between the gate and substrate
Q
dep= Charge in the depletion region
Threshold Voltage V TH !
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DIBL Definition!
If the devices with long channel lengths, the gate is completely responsible for depleting the semiconductor (Q B ).
In short channel devices, part of the
depletion is accomplished by the drain
and source bias. Since less gate voltage
is required to deplete (Q B ), the barrier
for electron injection from source to
drain decreases. This is known as drain
induced barrier lowering (DIBL)
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Effect of DIBL
Electrons have to overcome potential barrier to enter the channel
Ideal Situation: Potential barrier is only controlled by gate voltage
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Effect of DIBL
For a short-channel MOSFET, an increased drain-source voltage VDS lowers the source-to-channel potential barrier
No effect of VD for L>1m; but for L<1m, VD affects the barrier.
Short channel
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Effect of DIBL
V
Tis lowered due to effect of DIBL effect
Short channel
With increase VDS, VT is lowered, which results in increase in drain current ID and lower output impedance……
… affecting the gain GAIN of the device at given bias.
At 0.5m level, VTH reduction can be 100-200mV over the value in long channel limit, corresponding to potential increase in sub-thresold current by factors of 10 to 1000.
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Sub-threshold
When the surface is in weak inversion, a conducting channel starts to form and low level of current flows between source and drain
Sub-threshold current is the drain current for V GS <V T
Sub-threshold current depends
exponentially on V GS
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Threshold voltage VGS=VT where the exponential current dependence on VGS changes to linear (or quadratic) dependence
Sub-threshold
) V Kexp(V
ISUBTHRESOLD GS T
Strong inversion corresponds to values of gate overdrive of at least “several“ KT/q
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Useful region to operate the devices in low power application The sub-threshold slope is a feature of a MOSFET's current– voltage (ID Vs VG) characteristic.
A device characterized by steep sub-threshold slope (SS) exhibits a faster transition between OFF (low conduction) and ON (high conduction) states.
SS is limited to kT/q (60mV/dec) in MOS devices )
d(logI SS dV
D
GSVG Log ID
The SS shows the required gate voltage VG difference to the respective change in the drain current ID
S Slope (SS)
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Hot Carrier Effect
For sub-micron MOSFET, electron becomes “ hot ” due to strong E (electric field) 10 5 V/cm
“ Hot ” carriers may “ hit ” silicon atoms at high speed and cause impact ionization
The resulting electrons and holes are absorbed by the drain and substrate causing extra drain substrate current
Really “ hot ” carriers may be injected
into gate oxide and flow out of gate
causing gate current
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HCE
I
G
I
SUB
I
D39
HCE
n
+n
+n
-n
-LDS
LDD
n
+n
+IG
E is very high near the drain junction
LDD MOSFET is effective for reducing the E-field near drain junction #
Hot electron entered into the gate oxide and causes V
Tinstability (threshold drift).
# Due to lightly doped region (n- ) depletion region elongates and lower down the electric field.
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Body Effect
It is the effect caused due to a substrate bias V B (<V S )
In n-channel MOSFET negative substrate bias V B increases threshold voltage V T
the bulk-source P-N junction will be reverse bias
the depletion regions widens, and Q
Bincreases-V
THwill be increased
OX
B a
si
T
C
V V 4 qN ( )
OX B F
FB
T C
V Q
V 2
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SCBE results in an increased substrate potential and a decreased threshold voltage. This increases the drain current and decreases the MOSFET output resistances
SCBE
For electric field E>10 5 cm/sec an
avalanche process produces holes (1)
and creates a drift components of I sub
(2). This effect is called Substrate
Current-Induced Body Effect (SCBE)
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Overall Effect
V
DSR
OCLM
CLM+DIBL
HCE
SCEs strongly affect O/P
Impedance level
RF circuit
designer should clearly
understand their consequences