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ASIC for Biomedical Applications


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GOA - 403 206

JUNE 2004






I hereby state that this thesis for the Ph.D. degree on " ASIC for Biomedical Applications" is my original work and that it has not previously formed the basis for the award of any degree, diploma, associateship and fellowship or any other similar title to the best of my knowledge and information.

Shrutin A. Ulman (Candidate)


v s. (-; ‘.• • '


As required under the University ordinance, I certify that the thesis entitled

" ASIC for Biomedical Applications" submitted by Shrutin A. Ulman for the award of Doctor of Philosophy in Electronics is a research done by the candidate during the period of study under my tutelage and that it has not previously formed the basis for the award to the candidate of any degree, diploma, associateship, fellowship or other similar titles.

Head of Department, Department of Physics, Goa University.



I would like to express my sincere gratitude for the excellent guidance and advisement that Prof. A. B. Bhattacharyya has afforded me throughout my research career. The most important things that I have learned from him go far beyond electrical engineering topics. By putting me into the position to succeed, I believe I have and am poised to continue. He will remain as a role model throughout my career. I would also like to acknowledge Dr. G. R. Bhat, who has freely given of their time and assisted in the completion of this opus by giving advise in designing software.

I would like to thank Prof. P.R. Sarode, Head of the Department of Physics, Goa University, Goa, for extending the available experimental facilities during the course of the work.

I also would like to express my sincere thanks to Dr. Ajit Shirodkar for encouragement and support to pursue research in the field of VLSI design.

I am thankful to Prof. Y.S. Prahlad and Dr. J.A.E. De Sa, for encouragement and support in this work.

The technical support from the non-teaching staff of the Physics Department is very much appreciated.

Rev. Fr. P. M. Rodrigues, Director, Agnel Technical Education Complex, has been very kind in encouraging my research pursuits.


The most important support, both direct and indirect, that I have received is from my wife Dipali and daughter Simone, born during the work discussed in the dissertation. Dipali has handled the duties of spouse, friend, mother,

professional dietician , and home maker quite remarkably and adeptly while putting her own dreams on hold as I fulfilled mine.

My parents, Ashok and Asha Ulman, and sister Namrata have supported, encouraged, and loved me through all 30 years of formal education from the Mary Immaculate kindergarden class to the tutelage of my current advisor.

My mother-in-law, Meena Sarmalkar and sister-in-law, Monali have helped me complete my dissertation by providing a home for me , Dipali and Simone in the final and most crucial part of my thesis completion.


CONTENTS Chapter 1


1.1 Introduction to ASICs 2

1.2 Physics of Device Operation 7

1.3 Problem Statement 16

1.4 Physical MOSFET Modeling 19


1.6 A Simplified Methodology for the Extraction of the PREDICTMOS MOSFET Model Parameters

1.6.1 Introduction 29

1.6.2 Parameter Extraction of the PREDICTMOS Model Parameters from

the BSIM3 Model Parameters 31

1.6.3 Results And Discussion 37

1.6.4 Conclusion 40

1.6 References 42

Chapter 2


2.1 Introduction 44

2.2 Logic Levels 45

2.3 Analytical Expressions for Static Characteristics of Submicron CMOS

Inverters 48


2.3. 1 Introduction 48 2.3. 2 Expressions for the Static Characteristics of Submicron CMOS

Inverter 51

2.3. 3 Results and Discussion 55

2.3. 4 Conclusion 60

2.3 References 61

Chapter 3


3.1 Introduction 64

3.2 Propogation Delay Analysis of a Submicron CMOS Inverter using a

Physical and Predictive MOSFET model 65

3.2.1 Introduction 65

3.2.2 Derivation of Delay Expression for a Fast Ramp and Slow Ramp

Inputs 69

3.2.3 Simulation Results 75

3.2.4 Discussion 78

3.2.5 Conclusion 78

3.2 References 82

3.3 Delay Estimation for a Submicron CMOS Inverter Driving a CRC-Tr Interconnect Load

3.3. 1 Introduction 85


3.3. 3 Results and Discussion 95

3.3. 4 Conclusion 96

3.3 References 99

Chapter 4


4.1 Introduction 101

4.2 Short Circuit Power Dissipation of a CMOS Inverter Using the PREDICTMOS Model

4.2.1 Introduction 105

4.2.2 Short Circuit Power Dissipation Derivation 106

4.2.3 Results And Discussion 110

4.2.4 Conclusion 114

4.2 References 115

4.3 Transistor Sizing to Improve Performance and Power Budget

4.3. 1 Introduction 116

4.3. 2 Short channel short circuit power dissipation expression 117

4.3. 3 Results 124

4.3. 4 Discussion 125

4.3. 5 Conclusions 126

4.3 References 127


4.4 Macromodel for Short Circuit Power Dissipation of Submicron CMOS Inverters and Its Application to Design CMOS Buffers

4.4. 1 Introduction 128

4.4. 2 Derivation of a Macromodel 132

4.4. 3 Results and Discussion 134

4.4. 4 Conclusion 135

4.4 References 136

Chapter 5


5.1 Introduction 140

5.2 Device Speed 143

5.3 Delay Through Series Connected MOSFETS 145

5.3.1 Introduction 145

5.3.2 Delay Expression of S C M S 147

5.3.3 Results and Discussion 149

5.3 References 154

5.4 Comparative Evaluation of the Schmitt Trigger Architecture

5.4.1 Introduction 155

5.4.2 Design Methodology of the Three Schmitt Trigger's 156

5.4.3 Design Methodology of KST 159

5.4.4 Design Methodology of SSST 160


5.4.6 Discussion 164

5.4 References 166

5.5 A Physical Submicron MOSFET model Incorporating the Source/Drain Series Resistances and its Application to CMOS Inverter Delay


5.5.1 Introduction 167

5.5.2 Derivation of the Current Expression & Propagation Delay Model Incorporating the Source / Drain Series Resistance 168

5.5.3 Results 172

5.5.4 Discussion and Conclusion 173

5.5 References 175

5.6 Conclusion 177

Appendix 178

List of Publications 181



1.1 An Integrated Circuit 2

(a) A pin — grid array package (b) The silicon die is under the package lid

1.2 ASIC design flow 4

1.3 The N — MOSFET 7

1.4 Schematic of a MOSFET 20

1.5 Schematics of the drift and diffusion contributions 21

1.6 The I-V plot of a short channel MOST using BSIM3 34 1.7 A plot of the PREDICTMOS parameter vs versus L 36 1.8 Playback of I-V characteristics of 0.511 CMOS technology 39 1.9 The playback of the I-V characteristics of NMOSTs 42

Chapter 2

2.1 CMOS inverter 44

2.2 Logic Levels 45

2.3 Voltage Transfer Curve of a CMOS inverter 46

2.4 CMOS Inverter and its Voltage Transfer Curve showing five regions A to E 52

2.5 Static Characteristics of CMOS Inverter for a W/L of 311/0.611 forMOSFET Models BSIM 3, SPICE 3 and PREDICTMOS. 57


2.6 Variation of the logic threshold voltage with the 13N/13p ratio of the PREDICTMOS model benchmarked against BSIM 3 58

Chapter 3

3.1 Input and Output Voltage of a CMOS Inverter 70

3.2 CMOS inverter 70

3.3 Propagation Delay of a 0.6p. CMOS Inverter 80 3.4 Effect of scaling supply voltage on propagation delay 81

3.5 Inverter driving a CRC-it Load 89

3.6 Transient Response of a CMOS Inverter 91

Chapter 4

4.1 CMOS Inverters showing the parasitic capacitances Cpar, input gate capacitance C9 and the load capacitance CL 122

4.2 Psc/Pd Vs. Capacitive Load 138

4.3 Tapering Factor Vs. Short Circuit Power Delay Product showing Minima at

4.24 138

Chapter 5

5.1 MOSTs are connected in series discharge a capacitive load 147


5.2 Equivalent Inverter Circuit 148

5.3 Width of SCMS vs Delay 152

5.4 Optimization of top MOST for Minimum Delay 152

5.5 Conventional Schmitt Trigger 157

5.6 KST 159

5.7 Schmitt Trigger of M. Steyaert and W. Sansen 161



1.1 Definition of Common Parameters 13

1.2 The VT for the different channel dimensions of NMOST 37

1.3 Values of the Parameter vs 39

Chapter 2

2.1 Parameters of PREDICTMOS used for PMOS and NMOS devices 56 2.2 Effect of the Supply Voltage Scaling on the VGTR 58 2.3 VIA and VIH values benchmarked against BSIM 3v3 and SPICE 3 59

Chapter 3

3.1 Propagation Delay of a Submicron CMOS Inverter for varying Capacitive Loads and Input Ramps with L=0.6p, and W n=3g, 79 3.2 Propagation Delay of a 0.6g CMOS inverter for varying ramps 80 3.3 Propagation Delay of a 0.6p CMOS inverter driving RC interconnect80 3.4 Propagation Delay of a 0.6g CMOS inverter (CRC interconnect) 97

Chapter 4

4.1 Short Circuit Power Dissipation of 0.6p CMOS Inverter 111 4.2 Power dissipation of 0.6g CMOS inverter 111

4.3 Deviation of Models from SPICE 3 112



4.5 Short Circuit Power Dissipation of a Submicron CMOS Inverter for Varying capacitive Loads and Input Ramps with L=0.611 and W n=311 113

4.6 Psc for different Input Slew Rates 134

Chapter 5

5.1 Fall Times of Our Model Compared to SPICE 3 for varying CL. 150

5.2 Comparison of Signal Propagation Delay 150

5.3 Predicting The Accuracy of the Switching Point for CST 162 5.4 Predicting the Accuracy of the Switching Point for KST 163 5.5 Predicting the Accuracy of the Switching Point for KST 163 5.6 Predicting the Accuracy of the Switching Point for SSST 164 5.7 The Propagation Delay of the Three Schmitt Triggers 164 5.8 Comparison of the Three Schmitt Trigger Architectures 165 5.9 Comparison of Propagation Delay of a 0.511 CMOS inverter for varying

source / drain series resistance and capacitive loads 173






1.1 Introduction to ASICs

Motivation and Background:

An ASIC — is an application specific integrated circuit. Fig.1.1 shows an IC package (this is a pin grid array, or PGA, shown upside down, the pins will go through the holes in a printed circuit board). People often call the package a chip but as can be seen from Fig. 1.1(b), the silicon chip itself is mounted in a cavity under the sealed lid. A PGA package is usually made from a ceramic material, but plastic packages are also common.

(a) A pin — grid array package (b) The silicon die is under the package lid Fig. 1.1 An Integrated Circuit

The physical size of a silicon die varies from a few millimeters on a side to over 1 inch on a side, but instead we often measure the size of an IC by the number of logic gates or the number of transistors that an IC contains.[1.1.1]

The semiconductor industry has evolved from the first IC's of the early 1970s and matured rapidly since then. Early small scale integration IC's contained a few (1-10) logic gates amounting to a few tens of transistors. The era of medium scale integration packed even larger logic functions, such as the first microprocessors, onto a single chip. The era of very large scale integration now


arithmetic units well over a million transistors - on a single piece of silicon. As CMOS process technology improves, transistors continue to get smaller and ICs hold more and more transistors. The earliest IC's used bipolar technology as the MOS (metal oxide semiconductor) transistor was difficult to manufacture because of problems with the oxide interface. The introduction of polysilicon as the gate material in early 1980s was a major improvement in CMOS technology, making it easier to make two types of transistors, n - channel MOS and p - channel MOS transistors, on the same IC - a complementary MOS technology. The principal advantage of CMOS is low power consumption. Another advantage of a polysilicon gate was a simplification of the fabrication process, allowing devices to be scaled down in size [1.1.2].

An IC is also measured by the smallest feature size imprinted on the IC.

Transistor dimensions are measured in microns. A modern submicron CMOS process is now just as complicated as a submicron bipolar process. However, CMOS IC's have established a dominant position, are manufactured in much greater volume than any other technology, and therefore, because of the economy of scale, the cost of CMOS ICs is less than a bipolar IC for the same function.

With the advent of VLSI in the 1980s engineers began to realize the advantages of designing an IC that was customized or tailored to a particular system of application rather than using standard IC's alone. As VLSI became possible one could build a system from a smaller number of components by


Kil VHDLAhrilog netlist






logic cells

combining many standard IC's into a few custom IC's. Building a microelectronic system with a fewer IC's allows one to reduce cost and improve reliability [1.1.3].

IC's are made on a thin, circular, silicon wafer, with each wafer holding hundreds of die. The transistor and wiring are made from many layers built one on top of the other. Each successive mask layer has a pattern that is defined using a mask similar to a glass photographic slide. The first half a dozen or so layers define the transistors. The last half dozen or so layers define the metal wires between the transistors [1.1.4].

Design flow:

start Jr design entry

0 prelayout

sin Nation

logic synthesis

system partkioning

postlayout sin ulation

loorphnning CO



1W1-41 ciGuit

extraction routilg


netlist Fir friish

Fig 1.2 ASIC design flow


Fig 1.2 shows the sequence of steps to design an ASIC, called as a design flow.

The steps are listed below with a brief description of each step.

1. Design Entry: Enter the design into an ASIC design system, either using a hardware description language or schematic entry.

2. Logic Synthesis: Use an HDL and logic synthesis tool to produce a netlist.

3. System Partitioning: Divide a large system into ASIC sized pieces.

4. Prelayout Simulation: Check to see if the design functions correctly.

5. Floorplanning: Arrange the blocks of the netlist on the chip.

6. Placement: Decide the locations of cells in a block.

7. Routing: Make the connections between cells and blocks.

8. Extraction: Determine the resistance and capacitance of the interconnect.

9. Postlayout Simulation: Check to see the design still works with the added loads of the interconnect.


1.1 References

[1.1.1] J. D. Meindl, "Low power microelectronics: retrospect and prospect,"

Proceedings of the IEEE, vol. 83, no. 4, pp. 619-635, April 1995.

[1.1.2] Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, 1997 edition.

[1.1.3] Ken Martin, Digital Integrated Circuit Design, Oxford University Press, 2000.

[1.1.4] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, second edition. Reading, MA: Addison-Wesley, 1993.




C•I•I•M•I•I•I•I•I•I•I•I•I•2 D


1.2 Physics of Device Operation


The Fig.1.3 shows the cross section of a NFET. At room temperature, the N+ regions are ionized and consist of positively charged donor ions with freely mobile electrons. The substrate is P - type, consisting of negatively charged acceptor ions and mobile positive holes. At the P - N junction of the source and drain with the substrate, there is a dipole layer with positive charges on the side of the N-type region and negative charges in the P- type region, with a steady state potential difference between the N - type and P - type regions called as the diffusion potential [1.2.1].

The substrate surface between the source and the drain is called a channel, and in this case is a P - type. Therefore, the channel is not populated by electrons. If a positive voltage is applied to the gate, electrons are forced out from the source and drain into the channel, provided the force is strong enough to compensate the energy barrier of the diffusion potential. Secondly, holes must be expelled from the surface of the substrate before the conduction channel of


electrons is formed. To expel holes from the surface, extra gate voltage must be applied. Below the conducting electron channel is a layer of acceptor ions separating the electron channel from the substrate. The negatively charged acceptor ions sustains a potential (1)s, called the surface potential. The gate voltage necessary to form a conducing channel of electrons is called the threshold voltage VTH. If substrate doping is higher, more holes must be expelled from the surface before the channel is formed, and therefore the threshold voltage becomes higher. The threshold voltage is determined from the number of holes that must be expelled from the substrpte surface before a conducting channel is formed. Therefore, it depends on the size and the shape of the electrodes of the device. The effects are significant in scaled down CMOS and are known as short and narrow channel effects. When a voltage, VD, is applied between the source and the drain, a current ID, flows. When the gate voltage is small, electrons injected from the source to the channel diffuse to the drain and are collected by the reverse biased PN junction. This mechanism of channel current is called sub-threshold conduction. As the gate voltage increases, many electrons are pulled to the surface of the channel, and the channel current is a linear function of the gate voltage. The channel current, however, is not the linear function of drain voltage. The number of electrons in the channel decreases as the drain voltage increases, when the drain voltage equals the gate voltage, the rate of increase of the drain current is minimum and the channel current saturates [1.2.2].


When the gate and drain voltages are equal, the induced charge density vanishes at the drain's end of the channel. If the drain voltage is higher than the gate voltage, the channel terminates at the point somewhere between the source and drain. To the source side of this point, the electric field originates from the positive charge of the gate and terminates at the negative charges, which are electrons on the channel and ionized acceptors in the depletion region. To the drain side of point E, the electric field originates from the drain and terminates at,

a. The acceptor ions in the depletion region.

b. The charges on the gate electrodes.

c. The electrons injected from the end of the conducting channel.

The electric current between the end of the channel and the drain is carried on by static induction. Electrons in the channel of scaled CMOS FET are subject to a 104 — 105 V/cm field. At this high field, the drift velocity of electrons limits at the saturation velocity vsat.

The gate electrode is capacitively coupled to the other electrodes. In a self aligned process, there in an inevitable overlap of the gate to source and drain regions. When the voltage is small, the channel is non-existent, and the gate is capacitively coupled to the substrate. As the channel is formed, it shields the substrate from the gate. As the resistance in the channel is high, the channel is not at the same potential as the source and drain. The channel voltage follows the gate voltage, and through the channel the gate is still coupled to the substrate. When a channel is strongly formed, the substrate is shielded from the


gate, and the channel to substrate capacitance becomes a part of the source to substrate capacitance. [1.2.2]

Commonly estimated device parameters:[1.2.3]

A. Structural Parameters of a FET:

Fig. 1.3 shows the schematic of a FET. The contact size is set by the design rules. The thin oxide to contact hole design rule sets the minimum FET width. The drawn length of the polysilicon gate, Ldp, is set so that the electrical channel length, L, after taking due corrections for the out diffusion of the source and drain islands, is centered at the specified value.

Standard parameters used in the thesis are summarized in Table 1.1.

B. Gate Capacitance CG:

The gate capacitance of a minimum sized FET is estimated to be:

E OX L (k W

C G =


The channel of FET has capacitance to the substrate as well as to the gate.

The capacitance, CB, is given by the formula,

Ca =YE

S qN A LW 2V


where V is the channel to substrate potential plus the diffusion potential. The capacitance of the channel to the gate dominates over the capacitance to the substrate.

C. Drain Current:


Q - CG (VDD VT )

The average electric field is,

E. V DI) L

At this field if the drift velocity of electron is v. The drain current is,

I = (2


2 LL

where the factor 1/2 takes into account the non uniform charge of the channel.

D. Drain / Source Capacitance:

The capacitance of an abrupt PN junction formed within the semiconductor doped to NA acceptor per cubic centimeter is given by,

C= es qNA (1.6)


The capacitance of the vertical wall of the drain can be estimated by assigning the area that is the length of the periphery of the drain times the depth of the diffusion. Several corrections to equation (1.6) are included to improve the estimation of drain / source capacitance due to non-uniform doping [1.2.4].

E. Wiring Capacitance:

Metal wiring capacitance estimation becomes a major factor in determining the speed of VLSI circuits. The width of the metal wiring is usually about the same as the designed gate length, Ldp. The capacitance per unit length of the metal wire is,





E OX L dr f C MET =

Composite oxide thickness


where f is a non dimensional factor talking into account fringing field effects.

The design of semiconductor chips encompasses several separate, but often closely coupled, design activities. Today's system on a chip (SoC) development comprises of tasks such as design conceptualization, architectural design and optimization, logic synthesis, physical implementation and design verification.

Evolving design tools and design methodologies require changes in software design tool capabilities to meet current and future chip design needs.


Eox Es q p L L.' W WA, WD X MX


Table 1.1

DEFINITION OF COMMON PARAMETERS Dielectric constant of oxide (0.345 pF/cm)

Dielectric constant of silicon (1.06 pF/cm) Electronic charge (1.6 x 10 -19 C)

Carrier surface mobility (cm 2 / V.$) FET electrical channel length (cm)

FET designed channel length (cm) FET width (size) (cm)

Depletion layer thickness (cm) FET source / drain length (cm) Thin oxide thickness (cm)

Field oxide thickness (cm) Composite oxide thickness (cm) P — substrate doping (cm-3) N — substrate doping (cm -3) Power supply voltage (V) Gate Voltage (V)

Drainate Voltage (V) Substrate voltage (V)

FET threshold voltage (V) PFET threshold voltage (V) NFET threshold voltage (V)


VFB Flatband voltage (V)

(Ps Surface potential (V)

(PF Fermi level of substrate (V)

ID Drain current (A)

CG Gate capacitance (F, pF)

CB Substrate capacitance (F, pF)

CD Drain capacitance (F, pF)

COX cox/ Tox (F / cm 2)


1.2 References

[1.2.1] M. Shoji, CMOS Digital Circuit Technology, N. J. Prentice Hall, 1988.

[1.2.2] S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, Mc Graw Hill, 2 nd edition, 1999.

[1.2.3] R. Keyes, The physics of VLSI systems, Addition Wesley, September 1987.

[1.2.4] Mead, C. A. and Conway, L. , Introduction to VLSI systems, Addition Wesley, 1980.


1.3 Problem Statement

Chip Complexity and Cost is Rising — The job of IC design is becoming far more difficult and more expensive with each generation of process technology.

Chip complexity is increasing dramatically on many fronts — clock speeds, logic density, core complexity, package pin count and reduced power consumption all contribute to the manpower and time needed to produce a working chip.

Photomasks are a significant factor in chip cost, with mask sets costing around

$1M for a chip fabricated in a 130 nm CMOS process and increasing with each process advancement. As process nodes shrink, designers must more accurately model physically driven electrical effects that influence performance.

When developing IC's the chip designer must move between several different design activities, going between several abstraction levels, transitioning from higher to lower design representations and dealing with increasing design details along the way. Each design task requires the designer to use one or more design software packages, EDA tools, to accomplish the necessary design tasks.

One clear link of demarcation within chip design tasks is the separation of front end (logic) and backend (physical) design activities. The frontend / backend

"barrier" represents an important transition point for the designer, due to the importance of communicating design intent from logical to physical design representations. A successful transition from front end to backend design is necessary for achieving timing closure meeting the chips timing constraints without expensive and time consuming logic synthesis / physical implementation


A critical piece of the EDA tool suit is the logic synthesis. Almost every IC currently designed uses a logic synthesis tool to go from an RTL design representation, an architectural design view, to a gate — level representation, a structural design view. During this RTL to gate level transition, the synthesis tool also optimizes the chips design according to design constraint based on timing or area specification. It is this optimization that has led to a serious problem - a discontinuity in the handoff from logic to physical design. Logic synthesis is a tool for abstracting a gate level design representation from an RTL representation, according to timing constrains a designer would place on the design. The user of the logic synthesis tool would identify a library of gate level logic cells the synthesis tool would target along with the chips timing constraints.

To map the library into the design to meet timing constraints, the synthesis tools would use estimates of wiring loads on the various design nets, the so called estimated wire load model, based on the statistical lengths on each net.

Since the net parasitic loads were only estimates, the chips physical implantation, using place & route software tools, would yield an unpleasant surprise. The estimates were almost always much different from the timing delays the designer would get by extracting the wire lengths from the placed and routed chip and using this data to simulate the chips timing behavior. Along with poor initial timing estimation, logic optimization in synthesis also does a poor job handling incremental optimization changes — small changes can result in major design perturbations.


Non compliance of chip performance to the timing specification required the designer to modify the design at the RT level, re synthesize, and then redo the chips layout — expensive operations that took huge chunks of time. Adding to the design problem was the reality that you often needed more than one synthesis / P&R iteration to meet timing specifications- in other words, this design methodology has quickly become unacceptable, with shrinking time - to - market cycles and profit margins.

It is clear that the front end tools and methodologies designers currently use have several drawbacks:

They are inadequate for today's multimillion gate SOC.

They cannot adequately account for the process and physical details of ever shrinking process technologies.

They hinder, rather than help, designers achieve first pass silicon success.

Overcoming the front end discontinuity requires several changes in the way chip EDA tools operate and how they interfere with each other. Therefore one important change would be that the front end tools be based on physical and layout based models, so that the synthesis tools would be more efficient physical implementation tools.

This problem is addressed in this thesis. A compact, physical MOSFET model, PREDICTMOS, is adapted for circuit simulation. The model is based on layout and process parameters and hence would form the basis of an efficient front end tool for circuit simulation. This would provide the circuit


1.4 Physical MOSFET Modeling

Circuit simulation requirements are increasing due to scaling of MOSFET into the submicron range and system integration with many different functions on a single chip. These development trends furthermore force, due to cost-issues, standardization of fabrication process to merge different functions among different fabrication facilities including utilization of existing designs.

To assist in this development, the most important modeling issue is to guarantee sufficient simulation accuracy and applicability for any advanced technology. For achieving this task it is essential to maintain a physically correct modeling of the real technological origins of the effects that govern the function of these MOSFETs in simulating circuit operations.

Compact MOSFET models suffer from two contradictory requirements.

They should be as simple as possible and should be highly accurate at the same time. The basic equations for describing device characteristics are [1.4.1]:

> Poisson equation,

> Current density equation and

> Continuity equations.

These equations are simultaneously solved numerically in two dimensional (2—D) device simulators. On the other hand, these equations are solved analytically using transistor models for circuit simulation, yielding simplified descriptions for device performances.




s •




The origins of the device performances are three charges induced by the four terminals inside a transistor as shown in Fig. 1.4.


Fig. 1.4 Schematic of a MOSFET cross section with induced charge densities.

The bulk charge QB is the total charge in the depletion region. Q1 is the total inversion charge from which the drain current Ids is derived. Furthermore, Q1 is partitioned into two components - Qs (source charge) and QD (drain charge) according to dynamic operations [1.4.2].

Under the charge sheet approximation, and ignoring the charge distribution perpendicular to the surface, the terminal charges obtained are as follows:

Qa = w fQb (Y)dY


Q, = w fQ, (y)dy








/ Diffusion


I Drift / /



Fig. 1.5 Schematics of the drift and diffusion contributions to the total drain current Ids

L y QD =w j—

LQ. (Y)dY

0 QG = —(QB Q1) Qs =Qi —QD

where W and L are the width and the length of the channel respectively. The position dependent charges per unit area Qb and Qi along the channel are given under the assumption of a homogeneous substrate impurity distribution by,

Qb(Y)= —

cIN s

ub L D -

j[exPI— 13(0s

(Y) — Vbs )}+ 3()s (y) — V„ )— 1]


Q i (y) = —C ox (V G

O y )+ qN sub L 13 15 x [ex1 3 1— PO) , (Y) —

Vbs )1+



(Y) — V„ ) —

1S (1.14)




where Nsub, LD,


Vbs and VG' are the substrate doping, extrinsic Debye length, the inverse of the thermal voltage, surface potential, bulk voltage and the gate voltage minus the Hatband voltage respectively.

There charges have to be described analytically to develop a compact MOSFET model for circuit simulation [1.4.3]. Compact MOSFET models suffer from two contradictory requirements. They should be as simple as possible and should be highly accurate at the same time. Different approaches are used with the intention of finding an optimal solution between these requirements [1.4.4].

[1]. Numerical_Fitting_Models e.g SPICE and BSIM: [1.4.5] The models use look up tables based on mathematical description of device behaviour.

These models use numerical fitting parameters without any physical meaning. Numerical models have very high numerical efficiency and accuracy. However, they suffer from two drawbacks, their predictive ability is low and the effort required for parameters extraction is high.

[2]. Empirical_MOSFET_models e.g (Alpha Power Law Model): [1.4.6]. These models use empirical functions to describe physical effects. Physically motivated parameters are added as an after thought. They have moderate numerical accuracy and predictive ability. The effort required for parameter extraction is minimal.

[3]. Physics Based MOSFET Models: These models use closed form expressions to approximate device physics. They have a strong link to physical device parameters. Such models use as few fitting parameters as


models preserve a predictive ability which are useful for sensitivity analysis and the derivation of scaling rules e.g PREDICTMOS [1.4.7].

There are a multiplicity of MOSFET models reported in the literature apart from SPICE which have become the benchmark tool for circuit simulation. As SPICE is getting more and more empirical and predominantly numerical in solving circuit equations, compact models with physical basis and analytical capability are increasingly in demand.

The SPICE model has been dominating the field of device modeling due to the widespread use of numerical circuit simulators. In order to keep pace with rapid advancement in technology and associated miniaturization, SPICE models have become more and more empirical. This has necessitated the attempt to develop compact and physics based models. Further, the multiplicity of parameters in SPICE also leads to unacceptably long simulation time for modern complex systems. Hence, search is continuing for models which are described by less number of parameters. Last but not the least, with scaling of operating voltage, and demand for low power consumption devices operations in weak and moderate threshold are becoming more common. It appears that to meet diverse needs, the models are becoming more application specific than generic.

Some models (in public domain) which have found increasing acceptability, apart from SPICE, are

EKV Model [1.4.5]

ACM Model [1.4.5]

Alpha Power [1.4.6]


PREDICTMOS Model [1.4.7]

The essential features of the above models are:

EKV Model: It is symmetric and suited for analog design both in weak and strong inversion with a non physical fitting function connecting the weak and strong inversion region.

ACM Model: It is similar to EKV with an added advantage that it has a single piece expression which characterizes the MOSFET in strong, moderate and weak inversion.

Alpha Power Law Model: The model uses empirical functions to describe the MOSFET device physics.

The PREDICTMOS model was preferred over all the above models as it is a compact physical model.


1.4 References

[1.4.1] S.M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.

[1.4.2] N.D. Arora, MOSFET Models for VLSI Circuit Simulation. Berlin: Springer- Verlag, 1993.

[1.4.3] Y.P. Tsividis, Operation and Modeling of the MOS Transistor. New York:

McGraw-Hill, 1987.

[1.4.4] N.D. Arora, "Modeling and characterization of ultra deep submicron CMOS devices," IEICE Trans. Electron., vol. E82-C, pp. 967-975, 1999.

[1.4.5] D. Foty, MOSFET Modeling with SPICE: Principles and Practice.

Englewood Cliffs, NJ: Prentice-Hall, 1997.

[1.4.6] T. Sakura and P. Newton, "Alpha Power Law MOSFET model and its Application to CMOS Inverter Delay and Other Formulas", IEEE Journal of Solid State Circuits, Vol. SC-25, No. 2, pp 584 — 594, April 1990.

[1.4.7] A. Klos and A. Kostka, "PREDICTMOS-a Predictable Compact Model for Small geometry MOSFETs for circuit simulation and Device Scaling Calculations", Solid State Electronics, Vol. 44, pg. 1145-1156, 2000.


1 .5


The model equations for the geometry and voltage dependence of the threshold voltage were derived using a specially developed 2 - D technique for the solution of Poisson's equation in the channel region. The effects of short and narrow channel effects are calculated separately. The unified approach for the modeling of three effects simplifies their final superposition.

The model solves the Poisson's equation by decompositioning it into a 1-D inhomogeneous and a 2-D homogeneous part described by the Laplacian DEQ.

This equation is 2-D solved using conformal mapping techniques without the use of any unphysical fitting parameters. The modeling approach takes into account inhomogeneous doping profiles as well.

The model requires only two physically meaningful parameters to account for DIBL effects. One of these accounts for an inhomogeneous doping profile and the other depends on the shape of the source / drain function. The modeling of a narrow channel effect requires one additional parameter which considers the deeper space charge region at the channel sides and is independent of layout data.

In the PREDICTMOS model, the current equation is solved only with respect to the voltage V along the channel.


Ids = —ReffwQ,(y)-




The model has an exceptional predictive ability and gives a good approximation of the short and narrow channel effects on threshold voltage in submicron devices down to a channel length of about 0.1p. If the relative geometries in the devices are not changed, the limiting factors of the model will only be a noticeable occurrence of additional physical effects like velocity overshoot of the carriers or quantization effects due to high doping levels.

The PREDICTMOS model is based on the following approach:

• It divides the channel into the source and drain regions for the MOS transistor operating in the saturation mode. The gradual channel approximations are assumed to hold good in the source region where the standard inversion charge modeling equations are applicable.

• The drain saturation voltage is identified with a geometry and field independent parameter, Ep, at a channel position where the validity of the GCA region terminates.

• A high field region between the saturation voltage position and the drain terminal where (i) the gate loses control on the transport of carriers and (ii) the excess drain voltage over saturation (VDs-VDsAT) is dropped.


The PREDICTMOS model equation is given by,

ID WC" [(VGs

VT — C-5-)VD 2 SX 4- GS V — VDSX T DSX DS — V DSX


± VDS Vs







A Simplified Methodology for the Extraction of the PREDICTMOS MOSFET Model Parameters


The PREDICTMOS MODEL is a powerful tool for the simulation of submicron MOSFETs.The parameter extraction of the PREDICTMOS model should ideally be from the process and layout parameters which are provided by the foundry. The applications of the MODEL for circuit design analysis is attractive because the model being physics based is scalable and predicts the effect of technological parameters on circuit behavior. Most foundries provide the BSIM3 /SPICE 3 model parameters for circuit design. The section discusses a novel method of converting the BSIM3 parameters into the PREDICTMOS model parameters. Unlike the usual method of parameter extraction requiring expensive equipment, this method is based on mapping the BSIM3 model parameters to the PREDICTMOS parameters. A similar method can be adopted for the mapping of the SPICE3 model parameters to the PREDICTMOS parameters.

BSIM3 model parameters are most often provided for circuit design, in the submicron region. The BSIM3 model has about 120 parameters which model various effects of MOS transistor behavior. Circuit design using numerical models is tedious and computationally expensive. The aim of numerical models is to accurately reproduce circuit behavior once the model parameters have been fitted to a particular layout data. A major disadvantage of a numerical model is that these models do not lend themselves to large scale designs because the


circuit designer has to manage about 120 parameters, not all of which are layout or process based. BSIM3 MOSFET model uses a number of fitting parameters which increases the complexity of design expressions.

Physics based models have simpler design expressions in addition to having a strong link to process and layout parameters. Circuit designers can use a model such as PREDICTMOS which is physics based, scalable and has mathematically simple expressions [1.6.1]. Unfortunately such models are outside the reach of those designers who are not having a strong association with foundries. Many designers would find it advantageous to design a circuit for a particular technology to analyze the behavior of the circuit before assigning the design to a foundry.

Ideally the parameter extraction of the PREDICTMOS model is from the layout and process parameter data as explained in [1.6.2]. However in the absence of knowledge about the doping profile or the structure of the MOS transistor extracting the PREDICTMOS parameters is both arduous and obscure.

A simple and efficient method of extracting the PREDICTMOS parameters from the BSIM3 model parameter is in order. After parameter extraction, a playback of the MOS transistor curves with the PREDICTMOS model must accurately match those with the BSIM3 model.

Section 1.6.2 describes the method of parameter extraction and section 1.6.3 details the playback of the MOS transistor I-V curves using the PREDICTMOS model vis-a-vis the BSIM3 model. Section 1.6.4 concludes the


1.6. 2 PARAMETER EXTRACTION OF THE PREDICTMOS MODEL PARAMETERS FROM THE BSIM3 MODEL PARAMETERS 1. Threshold voltage (VT): The most important parameter to be mapped from the

BSIM3 model to the PREDICTMOS model is the threshold voltage. The extraction of this parameter from physical layout and process is explained in [1.6.2]. However without a knowledge of the process, doping profile and the MOSFET structure, the extraction of threshold voltage would not be accurate.

Fortunately most foundries provide the designer with:

a) VT of a small and narrow channel MOS transistor.

b) VT of a large and wide transistor.

c) VT of a small and wide transistor.

The definition of the VT in the PREDICTMOS model is

VT = V„ +go, +E, +E, +2E,v) C„


where, E0 stands for long channel electric field in the channel region, El s and

Eld represent the influence of the source and drain regions on this electric field and En,, covers a similar effect for transistors of smaller width. Eo, EIS, Eld and ESA, are functions of channel length, substrate doping concentration, gate oxide thickness and bias conditions. These functions are represented by closed form model equations which are nevertheless of a complex nature taking into account inhomogeneous doping profiles and other special MOSFET structure. For simplicity we can equate,


Eo +Eis +E_,,, +2E,,,, aL+PW —TIVDs (1.18)

where L and W are the effective length and effective widths respectively and a and 13 are coefficients which lump the effects of doping profile, gate oxide thickness and doping concentration i is the DIBL coefficient. The above approximation is valid because foundry extracts the threshold voltage by the process of binning wherein only the lengths and widths of the MOS transistor are varied. The foundry also furnishes the designer with the parameter VTHO,

which is a BSIM3 parameter, and

VTHO = V FB + q) i

where VFB is the flat band voltage and (pi is the surface inversion potential.

Therefore equation (1.17) can now be written as,

V, = V„HO + ES. [aL +13W - riV,„]



where, Es is the permitivity of silicon, Cox is the oxide capacitance and VDS is the source drain voltage. Three equations can be written from the VT values for different lengths and widths of the MOS transistor supplied by the foundry.

The last term on the right hand side can be ignored at this stage because it


we cannot assign it a value. Thus we have three equations in two unknowns a and 13 which can be solved simultaneously. Using this method the threshold voltage of a MOS transistors of any dimension can be estimated. The value of ri is estimated by curve fitting at the final stage during the playback of the characteristics of the MOS transistor.

2. Effective substrate factor: Once the threshold voltage is estimated the effective substrate factor is obtained from

V — V lc , = 111°

ir cOi V„ (1.20)

3. Square root approximation parameter: The square root approximation parameter to implement short channel effect is directly removed from BSIM3 as,

a ; =1+ ,0.5k

eff [1 1

p; + VSB a, +a2


+V„)] (1.21)

where al = 1.744 and a2 = 0.83.

4. Surface mobility: The calculation of the surface mobility is dependent on the estimation of the parameter 0. This parameter can be extracted from the I-V plot of a short channel MOS transistor using the BSIM3 model parameter as shown below,


VDS .Volts.)

Fig 1.6: The I-V plot of a short channel MOST using the BSIM3 MOSFET model.

The points A, B, and C represent the value of the current for different gate source voltages and when the MOST is operating in the linear mode i.e.

VDs<VDSAT• The current equation of a MOST in the linear mode is

I D gsliVCOX + Vps [vcs — NT, — ,11- Vim 1VDs 2


Using (1.22) and substituting A, B and C for ID at their respective VAS and VDS values, we get, three equations with a single unknown [is. we know from the PREDICTMOS model that the velocity saturation parameter, v sat-4-1.1x107

cm/s for short channel MOST. Using the average value of las in the expression,




1 + e(V„ — VT )+ 2k eff 94q3, + V„

We can estimate 0. The parameter 110 is given to the designer by the foundry.

This completes the extraction of the important PREDICTMOS parameters.

5. The other parameter like the effective width, the effective length, substrate and channel doping concentration, gate oxide thickness and source/drain junction depth are directly mapped from the BSIM model parameters,

provided by the foundry.

The extraction of the velocity saturation parameter for long channel MOSFETs involves measuring the velocity saturation parameter for different MOSFET lengths and plotting the curve of vs versus the channel length as shown below,






NGs —



71 1+ RS 1

± vsat



Vsat L

gs PS =0 (1.24)

VT )




Fig 1.7: A plot of the PREDICTMOS parameter vs versus the channel length L

The parameter vs can be estimated from the expression,

where Vsat=1.1x107 cm/s and y=1.3 for electrons and y=1 for holes the derivation of equation (8) is detailed in [1.6.1]. After linearising we get

vs = Vso + LVSL (1.25)

where Vso and VSL are linearising parameter from which vs can be estimated for different channel length.

6. The final stage of extraction involves generating the I-V plots of the MOS transistor and comparing them with the BSIM3 I-V plots. The parameter i is a fitting parameter and its value is chosen such that it gives the best fit between the two I-V plots.



The parameter extraction method detailed above is unorthodox but is well suited for quick parameter extraction. The results of extracting the above mentioned parameters are detailed below,

1. VT: I have used the BSIM3 model parameters supplied by MOSIS for 0.5R CMOS technology [1.6.3]. The VT for different channel dimensions as given by MOSIS are given in Table 1.2. The IDNGs curve for VTRO extraction is not required as the parameter is mapped directly from BSIM3.

Table 1.2

The VT for the different channel dimensions of NMOST Length (g) Width (.t) VT (V)

0.6 3 0.78

0.6 20 0.69

50 50 0.70

Using (3) and ignoring the \fps term, the three equations are, 0.6469722 + 4.43 x 10 -6 [aL + OW = 0.78

0.6469722 + 4.43 x 10-6 [aL + 8W = 0.69 0.6469722 + 4.43 x 10-6 [aL + 8W = 0.7

The corresponding values of the effective length and width are entered and the above equations are solved simultaneously to obtain the value of the parameters a and 13 as,


a = -4.0930 x 106 and 13 = 6.6131 x 106.

2. The effective substrate factor using (1.20) for a NMOS transistor of W/L of 311/0.6p. is 0.0689. the value of (pi was estimated from,

co, = 2 x 0.026 x log e n,

3. The square root approximation parameter using (1.21) was obtained as 1.022.

4. The estimation of the surface mobility was based on the method described in the previous section. The I-V plot of the NMOST was plotted and the three points were identified as A=323.5x10-6 amp, B=291x10-6 A and C=237x10-6

A at VDs=0.5V and at VGs=5V, VGs=4V and VGs=3V respectively. The surface mobility for the points A, B and C was estimated using (1.22) as !Asp,



;Ise = 213.26 and ii.sc = 273. From the i.ts values 0 was estimated using (1.23). The value of 0 obtained was 0.36.

5. The linearisation of vs versus the length of the NMOS transistor was the final parameter to be extracted using (1.24). The values of the parameter vs are given in the Table 1.3.


Table 1.3.

Values of the Parameter vs L(microns) vs (cm/s)

0.94 1.68 x 107 1.94 2.07 x 107 2.94 2.39 x 107 3.94 2.68 x 107

On linearising we can write, vs = VSO + LVSL

where VSO =1.39 x10' and V„ =3.32 x101°.

6. The final stage of extraction involves generating the I-V plots of the MOS transistors and comparing them with the BSIM3 I-V plots. The parameter rl and vs require a little tweaking to obtain the best match between the two I-V plots, as shown in Fig 1.8.

The parameter extraction technique detailed above gives an average error within 8% of the BSIM3 model. The error is the maximum in the region between the linear and the saturation regions and smoothing functions can be used to reduce this error [1.6.1]. Fig. 1.9 shows the I-V plots of NMOS transistors vis-à-vis BSIM3 plots for different aspect ratios.


-- SP

- PM

-1 V X 10-4




0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VAS

Fig. 1.8: Playback of I-V characteristics of 0.5p, CMOS technology wherein the Continuos line represents BSIM3 and the broken line PREDICTMOS.


One of the key objectives of the model is to evaluate the drain current depending on the voltages at the gate, drain, source and bulk. The variation of the drain current versus the voltages should be represented in three different ways as:

(a) Drain current versus the drain source voltage, as in Fig. 1.8, illustrates the maximum current available corresponding to a particular Nips and VGS.

(b) The drain current versus the gate source voltage, extracts the threshold voltage. In the methodology detailed above this is not necessary as the

VTHO is obtained from the BSIM3 model.

(c) The drain current (log) versus the gate source voltage, to demonstrate the


required in the above methodology as the PREDICTMOS model is predominantly used for modeling logic gates and hence used usually in strong inversion.

The parameter extraction technique detailed above gives an average error within 8% of the BSIM3 model values. The method helps us to extract the parameters for the PREDICTMOS model by using the I-V plots of the BSIM3 transistor model.

The extraction of the threshold voltage is the most crucial step. The credibility of the method to extract the threshold voltage arises from the fact that the method is based on the data provided by the foundry.

Though the method of parameter extraction detailed above can be labeled as semi — empirical, the model continues to maintain its physical basis, as all the parameters are layout and process parameters based. Most foundries do not give the PREDICTMOS model parameters and the above method permits the circuit designer to use the PREDICTMOS model for circuit design.


-0 50 0.5 x 10 2.5

4. + + + * *

_ - 0.5

04+ -4-4- -*-*- 4, 4-


2 2.5 3 3:5 4 4.5 5






[1.6.1] A Klos and A Kostka, "PREDICTMOS — a predictive compact model of small geometry MOSFETs for circuit simulation and device scaling calculation", Solid State Electronics, Vol. 44, pp. 1145 — 1156, 2000.

[1.6.21 A Klos and A Kostka, "A New Analytical Method of Solving the 2D Poisson's Equation in MOS Device Applied to Threshold Voltage and Subthreshold Modeling", Solid State Electronics, Vol. 39, No. 12, pp. 1761

— 1775, 1996.

[1.6.3] MOSIS Parametric Test Results, SPICE Model Parameters for Submicrometer Technologies obtained from www.mosis.org .


o as 1 1.5 2 2.5 3 a 5 4 4.5 VDS M

Fig.1.9 The playback of the I-V characteristics of NMOSTs with the W/L of 101.1/2[L and 201.1/0.611 respectively after parameter extraction from







2.1 Introduction

This chapter deals with the adaptation of the PREDICTMOS model to design static, complementary gates, which are the mainstay of CMOS design.

A static complementary gate is limited into a pullup network made of p- type transistors and a pulldown network made of n-type transistors. The gates output can be connected to VDD by the pullup network or Vss by the pulldown network. The two networks are complementary to ensure that the output is always connected to exactly one of the two power supply terminals at any time connecting the output to neither would cause an indeterminate logic value, but also a low resistance path from VDD to Vss. I have considered only the CMOS inverter as it forms the basic building block of CMOS digital circuit design and its structure is shown in Fig. 2.1



(input voltage) VOUT

(output voltage)


Fig. 2.1 CMOS inverter


Logic 1

Unknown (X)

Logic 0

2.2 Logic Levels

Since voltages are used to represent logic values, a relationship between the two should be established. As Fig. 2.2 shows, a range of voltages near VDD corresponds to logic 1 and a band around VSS corresponds to logic 0. the range in between is X, an unknown value. Although signals can swing through X while the chip is in operation, no mode must achieve X its final value.





Fig. 2.2 Logic Levels

A logic designer must be able to calculate the upper boundary of the logic zero and the lower boundary of the logic 1 region. Given a submicron logic gate design and process parameters, the designer must be able to guarantee that the maximum voltage produced for a logic zero will be some value VOL and that the minimum voltage produced for a logic zero will be VOH. These constraints also place limitations on the input voltages which will be interpreted as a logic zero (VII) and logic 1 (V)H).

The output voltages produced by a static, complementary gate are VDD and VSS, so the circuit designer knows that the output voltages will be






vni (V)

Slope = -1

acceptable. The real challenge is to compute the values of VIL and V,-{ and to do the computation, the values have to be defined. Fig 2.3 shows a transfer characteristics of an inverter with minimum size transistor for both pullup and pulldown. VIL and Viii are defined as the points at which the curves tangent has a slope of -1. Between these points the inverter has a high gain and outside that range the inverter has a gain less than 1.

The difference between Vol_ and VD.. (or between VoH and VIH ) is called the noise margin — the allowance zone that prevents the production of an illegal X output value.

Fig. 2.3 Voltage Transfer Curve of a CMOS inverter

As real circuits function under less — than — ideal conditions, the circuit designer must provide adequate noise margins to ensure that the chip operates reliably.

Noise could be introduced by,


• Off chip interconnections.

• Capacitive coupling to other electrical nodes.

• Variations in the power supply voltage.


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